Abstract: A multi-protocol receiver for receiving at least one input signal comprises: a comparator, a protection controller, and a multi-stage current mode logic (“CML”) buffer. The comparator compares a reference voltage and a predefined voltage. At least one output of the comparator is coupled to at least one input of the protection controller. The multi-stage current mode logic buffer receives the input signal and the reference voltage. Outputs of the protection controller are coupled to control inputs of the multi-stage CML buffer for operating the multi-stage CML buffer to process the input signal and the reference signal.

Abstract: A programmable clock divider having reset circuits configured to receive a DP count comprises a first flip-flop having a clock input, a first output, and one of the DP inputs configured to receive a clock signal, a plurality of flip-flops connected to form a ripple counter configured to each receive a DP input, a clock input, and a reset input to provide a first output coupled to the clock input of a subsequent flip-flop of the plurality of flip-flops, each subsequent flip-flop having its clock input coupled to the first output of the preceding flip-flop, a first reset circuit coupled to the flip-flops configured to provide an out signal in response to the flip-flops obtaining the DP count, and a second reset circuit configured to provide a reset signal to the reset input of the plurality of flip-flops in response to the out signal from the first reset circuit.

Abstract: A digital voltmeter, where a number of clock pulses for a first ramp voltage to reach an input voltage is determined. Next, a number of clock pulses for a second ramp voltage to reach the input voltage is determined. One of the first and the second ramp voltages having a least number of clock pulses to reach the input voltage is determined. A determination is made for a number of clock pulses for the determined one of the first and the second ramp voltages to reach a reference voltage. A digital code is generated for the input voltage based on the determined number of clock pulses for reaching the reference voltage and the determined least number of clock pulses for reaching the input voltage.

Abstract: A high-speed serial link receiver system, comprises: an input terminal for receiving a signal; a pi-coil including a first inductor, a second inductor, and a third inductor; a first electrostatic discharge device (“ESD”); a second ESD; an on-die-termination (“ODT”); and a receiver. The first inductor, the second inductor, and the third inductor are serially connected. The input terminal is coupled to the first inductor. A serial connection between the first inductor and the second inductor is coupled to the first ESD device. A serial connection between the second inductor and the third inductor is coupled to the ODT. The second ESD device and the receiver are coupled to the third inductor.

Abstract: A high-speed serial link receiver system, comprises: an input terminal for receiving a signal; a pi-coil including a first inductor, a second inductor, and a third inductor; a first electrostatic discharge device (“ESD”); a second ESD; an on-die-termination (“ODT”); and a receiver. The first inductor, the second inductor, and the third inductor are serially connected. The input terminal is coupled to the first inductor. A serial connection between the first inductor and the second inductor is coupled to the first ESD device. A serial connection between the second inductor and the third inductor is coupled to the ODT. The second ESD device and the receiver are coupled to the third inductor.

Abstract: A pulse-width-to-voltage (“PWV”) converter, comprises: a switch, a capacitor, a current source, and a current sink. The switch is operable by a signal. The current source, the current sink, and the switch are serially connected across a high voltage potential and a low voltage potential. An output node is coupled to a serial connection between the current source and the current sink. An end of the capacitor is coupled to the output node for converting a current into a control voltage indicative of a duty cycle of the signal.

Abstract: A multi-protocol receiver for receiving at least one input signal comprises: a comparator, a protection controller, and a multi-stage current mode logic (“CML”) buffer. The comparator compares a reference voltage and a predefined voltage. At least one output of the comparator is coupled to at least one input of the protection controller. The multi-stage current mode logic buffer receives the input signal and the reference voltage. Outputs of the protection controller are coupled to control inputs of the multi-stage CML buffer for operating the multi-stage CML buffer to process the input signal and the reference signal.

Abstract: A digital voltmeter, where a number of clock pulses for a first ramp voltage to reach an input voltage is determined. Next, a number of clock pulses for a second ramp voltage to reach the input voltage is determined. One of the first and the second ramp voltages having a least number of clock pulses to reach the input voltage is determined. A determination is made for a number of clock pulses for the determined one of the first and the second ramp voltages to reach a reference voltage. A digital code is generated for the input voltage based on the determined number of clock pulses for reaching the reference voltage and the determined least number of clock pulses for reaching the input voltage.

Abstract: A pulse-width-to-voltage (“PWV”) converter, comprises: a switch, a capacitor, a current source, and a current sink. The switch is operable by a signal. The current source, the current sink, and the switch are serially connected across a high voltage potential and a low voltage potential. An output node is coupled to a serial connection between the current source and the current sink. An end of the capacitor is coupled to the output node for converting a current into a control voltage indicative of a duty cycle of the signal.

Abstract: A power voltage detector comprises voltage sensors for sensing supply voltages; and a logic. The logic combines the sensed supply voltages to generate a logic output indicative of whether the sensed supply voltages have met one or more predefined thresholds. Each of the voltage sensors has diode-connected transistors and passive resistance. The diode-connected transistors and the passive resistance are serially connected for generating an output, where the output is coupled to an input of the logic.

Abstract: A bandgap reference voltage generator, comprises: a bias circuit configured to generate a start signal; a startup circuit having at least two serially-connected transistors configured to receive the start signal; a proportional-to-absolute-temperature (“PTAT”) generation circuit having a first current mirror, an amplifier, a resistor, and transistors; and a complementary-to-absolute-temperature (“CTAT”) generation circuit having a second current mirror, a passive network of resistors, and at least one transistor. The at least two serially-connected transistors are connected across a first input of the amplifier and a second input of the amplifier. An output of the amplifier is coupled to the first current mirror and the second current mirror. The passive network of resistors is coupled across outputs of the second current mirror. The CTAT generation circuit has an output node for outputting a bandgap reference voltage.

Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.

Abstract: An optimized method, system, and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.

Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) and at least one slave delay locked loop (“SDLL”). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.

Abstract: A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.

Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.

Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) and at least one slave delay locked loop (“SDLL”). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.

Abstract: An optimized method, system, and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.

Abstract: An optimized method and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.

Abstract: A duty cycle detection circuit, comprises a charge storage component and compare logic. The charge storage component has at least one capacitor, at least one switch, and, at least one current source. A clock signal is used to operate the at least one switch for charging the at least one capacitor using the at least one current source. The charge storage component outputs a first signal indicative of an amount of charge stored when the clock signal is logic high and a second signal indicative of an amount of charge stored when the clock signal is logic low. The compare logic compares the first signal and the second signal to determine a duty cycle for the clock signal.