Abstract: An example semiconductor processing system may include a chamber body having sidewalls and a base. The processing system may also include a substrate support extending through the base of the chamber body. The substrate support may include a support platen configured to support a semiconductor substrate, and a shaft coupled with the support platen. The processing system may further include a plate coupled with the shaft of the substrate support. The plate may have an emissivity greater than 0.5. In some embodiments, the plate may include a radiation shied disposed proximate the support platen. In some embodiments, the plate may include a pumping plate disposed proximate the base of the chamber body. In some embodiments, the emissivity of the plate may range between about 0.5 and about 0.95.

Abstract: Exemplary substrate support assemblies include an electrostatic chuck body defining a substrate platform. The substrate platform may be characterized by an upper surface. The platform may define a purge aperture. The platform may include a plurality of mesas that are disposed in an inner region of the upper surface. Each of the mesas may protrude upward from the upper surface. The platform may include a sealing band that extends upward from the upper surface in a circumferential pattern and partially encircles the inner region of the upper surface. Top surfaces of the mesas and sealing band may form a support surface for a substrate. The sealing band may define a number of gaps. The assemblies may include a support stem coupled with the electrostatic chuck body, a heater embedded within the electrostatic chuck body, and a backside gas source that is coupled with the purge aperture of the support surface.

Abstract: Exemplary semiconductor processing chambers include a chamber body defining a processing region. The chambers may include a substrate support disposed within the processing region. The substrate support may have an upper surface that defines a recessed substrate seat. The chambers may include a shadow ring disposed above the substrate seat and the upper surface. The shadow ring may extend about a peripheral edge of the substrate seat. The chambers may include bevel purge openings defined within the substrate support proximate the peripheral edge. A bottom surface of the shadow ring may be spaced apart from a top surface of the upper surface to form a purge gas flow path that extends from the bevel purge openings along the shadow ring. A space formed between the shadow ring and the substrate seat may define a process gas flow path. The gas flow paths may be in fluid communication with one another.

Abstract: Exemplary semiconductor processing systems may include a chamber body including sidewalls and a base. The system may include a substrate support extending through the base of the chamber body. The chamber body may define an access circumferentially extending about the substrate support at the base of the chamber body. The system may include one or more isolators disposed within the chamber body. The one or more isolators may define an exhaust path between the one or more isolators and the chamber body. The exhaust path may extend to the base of the chamber body. The systems may include a fluid source fluidly coupled with the chamber body at the access extending about the substrate support.

Abstract: Exemplary substrate support assemblies include an electrostatic chuck body defining a substrate platform. The substrate platform may be characterized by an upper surface. The platform may define a purge aperture. The platform may include a plurality of mesas that are disposed in an inner region of the upper surface. Each of the mesas may protrude upward from the upper surface. The platform may include a sealing band that extends upward from the upper surface in a circumferential pattern and partially encircles the inner region of the upper surface. Top surfaces of the mesas and sealing band may form a support surface for a substrate. The sealing band may define a number of gaps. The assemblies may include a support stem coupled with the electrostatic chuck body, a heater embedded within the electrostatic chuck body, and a backside gas source that is coupled with the purge aperture of the support surface.

Abstract: Semiconductor processing systems according to embodiments of the present technology may include a chamber body having sidewalls and a base. The chamber body may define an internal volume. The systems may include a substrate support assembly having a shaft and a platen coupled with the shaft along a first surface of the platen. The semiconductor processing systems may include a cover plate positioned on the platen of the substrate support assembly along a second surface of the platen opposite the first surface. The cover plate may include a flange extending about an exterior region of the cover plate. The flange may be in direct contact with the platen. The cover plate may include an upper wall vertically offset from the flange. An interior volume may be defined between the upper wall and the platen of the substrate support assembly.

Abstract: A semiconductor processing system includes a remote plasma source (RPS), a faceplate, and an output manifold positioned between the RPS and the faceplate. The output manifold is characterized by a plurality of purge outlets that are fluidly coupled with a purge gas source and a plurality of deposition outlets that are fluidly coupled with a deposition gas source. A delivery tube extends between and fluidly couples the RPS and the faceplate. The delivery tube is characterized by a generally cylindrical sidewall that defines an upper plurality of apertures that are arranged in a radial pattern. Each of the upper apertures is fluidly coupled with one of the purge outlets. The generally cylindrical sidewall defines a lower plurality of apertures that are arranged in a radial pattern and below the upper plurality of apertures. Each of the lower apertures is fluidly coupled with one of the deposition outlets.

Abstract: Exemplary semiconductor processing chambers may include a faceplate assembly characterized by at least one surface defining a number of voids. Each void is configured to receive an interchangeable thermal body that can be selected from multiple interchangeable thermal bodies. Exemplary semiconductor processing chambers may also include a gas box characterized by movable members. Each movable member is configured to engage a delivery port and is movable to provide flow control for a gas being delivered to the processing volume through a gas flow path. Zoned flow and/or temperature control may be provided by the faceplate assembly, the gas box, or both.

Abstract: Exemplary semiconductor processing systems may include a chamber body including sidewalls and a base. The chamber body may define an interior volume. The processing systems may include a substrate support extending through the base of the chamber body. The substrate support may be configured to support a substrate within the interior volume. The processing systems may include a faceplate positioned within the interior volume of the chamber body. The faceplate may define a plurality of apertures through the faceplate. The processing systems may include a faceplate heater seated on the faceplate. The faceplate heater may include a first heater coil extending proximate a first area of the faceplate. The faceplate heater may include a second heater coil extending proximate a second area of the faceplate.

Abstract: Exemplary support assemblies may include an electrostatic chuck body defining a substrate support surface. The substrate support assemblies may include a support stem coupled with the electrostatic chuck body. The substrate support assemblies may include a heater embedded within the electrostatic chuck body. The substrate support assemblies may include an electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The substrate support assembly may include a ceramic material characterized by a grain size of less than or about 5 ?m.

Abstract: Exemplary semiconductor processing chambers may include a chamber body including sidewalls and a base. The chambers may include a substrate support extending through the base of the chamber body. The substrate support may include a support platen configured to support a semiconductor substrate. The substrate support may include a shaft coupled with the support platen. The substrate support may include a shield coupled with the shaft of the substrate support. The shield may include a plurality of apertures defined through the shield. The substrate support may include a block seated in an aperture of the shield.

Abstract: An example semiconductor processing system may include a chamber body having sidewalls and a base. The processing system may also include a substrate support extending through the base of the chamber body. The substrate support may include a support platen configured to support a semiconductor substrate, and a shaft coupled with the support platen. The processing system may further include a plate coupled with the shaft of the substrate support. The plate may have an emissivity greater than 0.5. In some embodiments, the plate may include a radiation shied disposed proximate the support platen. In some embodiments, the plate may include a pumping plate disposed proximate the base of the chamber body. In some embodiments, the emissivity of the plate may range between about 0.5 and about 0.95.

Abstract: A plasma processing system is described. The system may include a showerhead. The system may further include a first RF generator in electrical communication with the showerhead. The first RF generator may be configured to deliver a first voltage at a first frequency to the showerhead. Additionally, the system may include a second RF generator in electrical communication with a pedestal. The second RF generator may be configured to deliver a second voltage at a second frequency to the pedestal. The second frequency may be less than the first frequency. The system may also include a terminator in electrical communication with the showerhead. The terminator may provide a path to ground for the second voltage. Methods of depositing material using the plasma processing system are described. A method of seasoning a chamber by depositing silicon oxide and silicon nitride on the wall of the chamber is also described.

Abstract: Exemplary semiconductor processing chambers may include an inlet manifold defining a central aperture. The inlet manifold may also define a first channel and a second channel, and each of the channels may extend through the inlet manifold radially outward of the central aperture. The chambers may also include a gasbox characterized by a first surface facing the inlet manifold and a second surface opposite the first. The gasbox may define a central aperture aligned with the central aperture of the inlet manifold. The gasbox may define a first annular channel in the first surface extending about the central aperture of the gasbox and fluidly coupled with the first channel of the inlet manifold. The gasbox may define a second annular channel extending radially outward of the first and fluidly coupled with the second channel of the inlet manifold. The second annular channel may be fluidly isolated from the first.

Abstract: Exemplary methods of semiconductor processing may include treating a surface of a substrate with a hydrogen-containing precursor. The substrate may be disposed within a processing region of a semiconductor processing chamber. The methods may include contacting the substrate with a tungsten-containing precursor. The methods may include forming an initiation layer comprising tungsten on the substrate. The methods may include treating the initiation layer with a hydrogen-containing precursor. The methods may include forming a plasma of the tungsten-containing precursor and a carbon-containing precursor. Hydrogen in the plasma may be limited to hydrogen included in the carbon-containing precursor. The methods may include forming a tungsten-containing hardmask layer on the initiation layer.

Abstract: Exemplary methods of semiconductor processing may include forming a silicon oxide material on exposed surfaces of a processing region of a semiconductor processing chamber. The methods may include forming a silicon nitride material overlying the silicon oxide material. The methods may include performing a deposition process on a semiconductor substrate disposed within the processing region of the semiconductor processing chamber. The methods may include performing a chamber cleaning process.

Abstract: One or more embodiments described herein generally relate to selective deposition of substrates in semiconductor processes. In these embodiments, a precursor is delivered to a process region of a process chamber. A plasma is generated by delivering RF power to an electrode within a substrate support surface of a substrate support disposed in the process region of the process chamber. In embodiments described herein, delivering the RF power at a high power range, such as greater than 4.5 kW, advantageously leads to greater plasma coupling to the electrode, resulting in selective deposition to the substrate, eliminating deposition on other process chamber areas such as the process chamber side walls. As such, less process chamber cleans are necessary, leading to less time between depositions, increasing throughput and making the process more cost-effective.

Abstract: A substrate pedestal includes a thermally conductive substrate support including a mesh, a thermally conductive shaft including a plurality of conductive rods therein, each conductive rod having a first end and a second end, and a sensor. The first end of each conductive rod is electrically coupled to the mesh, and the sensor is disposed between the first and second ends of each conductive rod and configured to detect current flow through each conductive rod.

Abstract: One or more embodiments described herein generally relate to methods for chucking and de-chucking a substrate to/from an electrostatic chuck used in a semiconductor processing system. Generally, in embodiments described herein, the method includes: (1) applying a first voltage from a direct current (DC) power source to an electrode disposed within a pedestal; (2) introducing process gases into a process chamber; (3) applying power from a radio frequency (RF) power source to a showerhead; (4) performing a process on the substrate; (5) stopping application of the RF power; (6) removing the process gases from the process chamber; and (7) stopping applying the DC power.

Abstract: Embodiments described herein relate to methods and tools for monitoring electrostatic chucking performance. A performance test is performed that requires only one bowed substrate and one reference substrate. To run the test, the reference substrate is positioned on an electrostatic chuck in a process chamber and the bowed substrate is positioned on the reference substrate. A voltage is applied from a power source to the electrostatic chuck, generating an electrostatic chucking force to secure the bowed substrate to the reference substrate. Thereafter, the applied voltage is decreased incrementally until the electrostatic chucking force is too weak to maintain the bowed substrate in flat form, resulting in dechucking of the bowed wafer. By monitoring the impedance of the chamber during deposition using a sensor, the dechucking threshold voltage can be identified at the point where the impedance of the reference substrate and the impedance of the bowed substrate deviates.