Patents by Inventor Venkatesh Prasad

Venkatesh Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134717
    Abstract: An approach for managing workload deployment in a distributed network, including edge computing is provided. The approach includes deploying several modules, such as, EMM (energy management module), LDM (localized deployment manager) and EDM (edge deployment manager). These modules will be constantly monitoring and managing the energy consumption at the edge nodes under their purview and communicate with other modules to develop a holistic energy management system (e.g., energy policies, energy algorithms, energy plans, etc.) to ensure the most effective energy management of workload is implemented.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 25, 2024
    Inventors: Mathews Thomas, Utpal Mangla, Sai Srinivas Gorti, Sharath Prasad Krishna Prasad, Venkatesh Ashok Rao Rao, Praveen Jayachandran, Eric Lee Gose, Juel Daniel Raju, Amandeep Singh
  • Publication number: 20240092168
    Abstract: Systems and methods are described for operating a peripheral device of a vehicle. Control circuitry determines whether the peripheral device is connected to a vehicle controller. Control circuitry receives operational settings for the peripheral device, e.g., in response to determining that the peripheral device is connected to the vehicle controller. The vehicle controller is used to control the peripheral device using the received operational settings.
    Type: Application
    Filed: September 19, 2022
    Publication date: March 21, 2024
    Inventors: Benjamin Moffatt, Ian Salsbury, Yasmin Jawad, Sheraz Atid, Tithal Bhandari, Joseph Hornby, Sanketh S. Venkatesh Prasad
  • Publication number: 20240071519
    Abstract: The disclosure provides circuits and methods for increasing NAND input/output (I/O) bandwidth during read/write operations. The method includes transmitting a clock signal between a controller I/O circuit and a memory I/O circuit along a read enable bus, transmitting 8 bits of data along an I/O bus, and transmitting 2 bits of data along a data strobe signal (DQS) bus. Transmitting 2 bits of data along the DQS bus includes transmitting a first DQS data signal along the DQS bus and transmitting a first inverse DQS data signal along the DQS bus.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: TIANYU TANG, Venkatesh Prasad Ramachandra, Siddhesh Darne
  • Patent number: 11905152
    Abstract: Traditionally, counterweight fork type autonomous mobile robots (AMR) have been used for any kind of pallet. But the challenge is it occupies lot more maneuvering space while making turns, which cannot work in narrow operating zones. Hence fork over AMR is preferred. However, these fork over AMR have extended parts always touching the ground surface and thus are not suitable for pallets with a wooden plank at the bottom of the fork opening in the pallet. To overcome the above technical problems, an Adjustable Counterweight-based Fork Type Autonomous Mobile Robot (ACFTAMR) is provided that includes chassis assembly and vertical mast unit, a horizontal cross slide mechanism and forks. The chassis assembly is provided counterweight assembly and counterbalance shafts that move forward and backward during pickup and release of payload when the vertical mast unit moves in upward/downward direction, thus providing better stability and counterbalance to the ACFTAMR.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: February 20, 2024
    Assignee: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Venkatesh Prasad Bangalore Srinivas, Pradeepak Rajendran, Sreehari Kumar Bhogineni
  • Patent number: 11904774
    Abstract: Wiper is utilized to clean side-view mirror of a vehicle. Existing wiper attached with the side-view mirror obstructs visibility of a driver while cleaning the side-view mirror in a rainy season or in a dusty environment, which leads to an accident. A vehicle mirror wiping unit is provided. The vehicle mirror wiping unit includes a mirror; a mirror shutter assembly; a mirror casing; a mirror mounting unit, consisting of: the mirror, a mirror spring, a spring retaining cap, and a mirror spring holder; a pin pass through a cut-out of the spring retaining cap, and a cut-out in the mirror spring holder; and a cleaning elastomer is triggered by the mirror shutter motor, and the mirror shutter moves from the first end of the mirror to the second end of the mirror. A frontal surface of the mirror shutter is a reflective surface functioning as a mirror.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: February 20, 2024
    Assignee: Tata Consultancy Services Limited
    Inventors: Venkatesh Prasad Bangalore Srinivas, Vivek Kumar
  • Patent number: 11891289
    Abstract: There is huge demand for automation in manufacturing, logistics, postal, distribution centers, ecommerce, retail. Typical scissor lift designs can carry large payload but are larger in size. There is a need for a compact fork with more payload carrying capacity. The dual side actuated scissor fork type lift unit is provided. The dual side actuated scissor fork type lift unit includes a top plate, a bottom plate, one or more linear motion (LM) blocks mounted on one or more linear guides, one or more mounting blocks mounted on the one or more LM blocks, and slot on a first end of at least one actuation link is connected to the bottom plate through a pin. The one or more LM blocks is free to slide on the one or more linear guides. The one or more mounting blocks moves along with a motion of the one or more LM blocks.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: February 6, 2024
    Assignee: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Venkatesh Prasad Bangalore Srinivas, Sreehari Kumar Bhogineni
  • Publication number: 20240037148
    Abstract: Disclosed herein is a computer-implemented method for the ingestion of data into a partitioned database, the method comprising: receiving data at at least one ingestion node of a graph database, storing the data as a disjoint set of vertices, in a partitioned database, analyzing the disjoint set of vertices to find a set of remote edges and a set of native edges, and storing the set of remote edges and the set of native edges as a set of disjointed vertices in the partitioned database.
    Type: Application
    Filed: July 27, 2022
    Publication date: February 1, 2024
    Applicant: VMware, Inc.
    Inventors: Sripriya Venkatesh PRASAD, Deep P DESAI
  • Patent number: 11888310
    Abstract: Methods and apparatus to monitor the precharging of high voltage circuits are disclosed. In one embodiment, an apparatus includes a switch that selectively enables or disables precharge current to a high voltage circuit based on a switch control signal. The apparatus also includes a comparison circuit that compares a scaled version of a circuit voltage to a reference voltage to generate the switch control signal. In one embodiment, the switch control signal is generated to enable the precharge current when the scaled version of the circuit voltage is greater than the reference voltage.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: January 30, 2024
    Assignee: Motiv Power Systems, Inc.
    Inventors: Venkatesh Prasad Hanglur Narasimha, James Michael Castelaz
  • Publication number: 20240030728
    Abstract: The present disclosure describes an automated docking system for charging chargeable mobile devices. Conventionally, docking systems utilize expensive technology like wireless charging leading to higher cost. The system of the present disclosure provides a cost effective generic docking station with internet of things (IoT) interface for heterogeneous chargeable mobile devices which leads to precise docking. The generic design of the docking station enables docking different category of the chargeable mobile devices such as fork type, unit load type, at same docking station with different charging currents. IoT enabled docking station communicates with the chargeable mobile devices and charges them based on battery health, quick/slow charge, category, task duration and/or the like. The present disclosure brings a design flexibility to the docking station and contact pads, so that the flexible design adjusts itself in translation and rotation axis for certain degrees of freedom if there is an error in docking.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 25, 2024
    Applicant: Tata Consultancy Services Limited
    Inventors: VENKAT RAJU CHINTALAPALLI PATTA, VENKATESH PRASAD BANGALORE SRINIVAS, PRADEEP PRABHAKAR KAMBLE, SWAPNIL SUNIL KALHAPURE, SREEHARI KUMAR BHOGINENI
  • Patent number: 11870240
    Abstract: An eFuse for use in high voltage applications is disclosed. In one embodiment, an apparatus includes a solid-state switch having source and drain terminals connected to switch a load current from a high voltage source through a high voltage load. The apparatus also includes a sense circuit that senses a voltage between the switch source and drain terminals and turns off the switch when the voltage exceeds a selected voltage level.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: January 9, 2024
    Assignee: Motiv Power Systems, Inc.
    Inventors: Venkatesh Prasad Hanglur Narasimha, James Michael Castelaz
  • Patent number: 11869619
    Abstract: Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: January 9, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jang Woo Lee, Srinivas Rajendra, Anil Pai, Venkatesh Prasad Ramachandra
  • Patent number: 11851311
    Abstract: Material handling of packed goods on pallets, roller cages within facilities is in huge volumes and consumes lot of operators' time and efforts. Embodiments of the present disclosure provide an autonomous payload handling apparatus (APHA) that addresses the above material handling process by automating with an intelligent modular robotic platform. The APHA includes fork assemblies that slides alongside of the pallet for better balance over payload and maintains smooth navigation. The fork assemblies equipped with contact/vision sensors that enable APHA to determine whether there is any offset or any contact between surfaces of APHA and/or pallet. The fork assemblies capture sensor data of surrounding object(s) during navigation, size of payload, and pallet, etc. The captured sensor data enables the APHA to correct its offset and/or compute a mode of approach (e.g., navigating angle, deviating from obstacle(s), sliding through pallet/roller cages, and the like) to handle payload(s).
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: December 26, 2023
    Assignee: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Venkat Raju Chintalapallipatta, Venkatesh Prasad Bangalore Srinivas, Pradeep Prabhakar Kamble, Sri Sai Shyam Siddharth Gollu, Sreehari Kumar Bhogineni
  • Publication number: 20230399212
    Abstract: Conventional fork type autonomous mobile robots (AMRs) are suitable to handle pallets and are typically designed with two forks. Such AMRs are very bulky and designed for a cart handling application, and usually have large openings and less suitable for lifting roller carts. Present disclosure provides chassis with integrated single fork assembly for AMRs/Autonomous Guided Vehicles (AGVs) for transporting roller cages/carts within warehouses. Chassis with integrated single fork assembly enables performing tasks given by end users. Chassis carries steer and drive wheel and swivel wheels to increase stability of the AMR wherein a fork mechanism is provided which includes fork wheels and lifting mechanism.
    Type: Application
    Filed: August 22, 2022
    Publication date: December 14, 2023
    Applicant: Tata Consultancy Services Limited
    Inventors: Venkatesh Prasad BANGALORE SRINIVAS, Pradeep Prabhakar Kamble
  • Patent number: 11840437
    Abstract: Conventional fork-type autonomous mobile robots (AMRs) have been suited to handle pallets and are typically designed with two forks. Such AMRs are very bulky in nature and specifically designed for a cart handling application, and usually have large openings and less suitable for lifting roller carts. Present disclosure provides a fork assembly for AMRs/Autonomous Guided Vehicles (AGVs) for transporting roller cages/carts within warehouses. The fork assembly when integrated with AMR enables performing various tasks. More specifically, the fork assembly includes a first plate and a second plate. The fork assembly further include roller movement enabler blocks that are driven by respective fork motors. Movement of the roller movement enabler blocks enable rolling of rollers on respective roller guides within tapered region thereby enable lowering and rising of the second plate with reference to the first plate for lifting a payload and movement thereof to a desired location.
    Type: Grant
    Filed: June 14, 2023
    Date of Patent: December 12, 2023
    Assignee: Tata Consultancy Services Limited
    Inventors: Venkatesh Prasad Bangalore Srinivas, Raghav Ponnath
  • Publication number: 20230395108
    Abstract: Systems and methods disclosed herein provide for selectively activating or deactivating one or more memory of a memory array, such that related data path logic of deactivated memory dies neither detects nor processes control signals or data signals for data operations. Examples of the systems and methods provided herein operate to detect a first enable signal at a memory die and detect a first data signal on input/output (I/O) receivers of the memory die. Responsive to detecting at least the first enable signal, a bit value encoded in the first data signal is latched to obtain a first bit pattern. A second bit pattern is obtained, and, based on a comparison of the first bit pattern to the second bit pattern, the I/O receivers of the memory die are activated.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Inventors: SNEHA BHATIA, Sajal Mittal, Venkatesh Prasad Ramachandra, Anil Pai
  • Publication number: 20230386531
    Abstract: A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second enable signals and utilizes rising or falling edges of a clock signal to latch the encoded bit information, which can then be decoded to determine corresponding command and address codes. A chip select sequence is also disclosed that enables a memory chip configuration to be employed in which each chip in a package shares a common connection to a controller but does not require hard-coded pins for performing chip select.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Inventors: TIANYU TANG, Siddhesh Darne, Venkatesh Prasad Ramachandra
  • Publication number: 20230386600
    Abstract: Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Inventors: Jang Woo Lee, Srinivas Rajendra, Anil Pai, Venkatesh Prasad Ramachandra
  • Publication number: 20230386584
    Abstract: Systems and methods are provided for correcting errors in unmatched memory devices. Various embodiments herein train a memory interface to determine a duty cycle timing for a clock signal in a data window formed by a data signal in a memory cell. The duty cycle timing identifies an initial trained timing in the data window at which a setup portion and a hold portion of the data window are approximately equal in length when the trigger signal is received at the initial trained timing. The embodiments herein also identify an event that shifts the duty cycle timing away from the initial trained timing, and triggers a retraining of the memory interface based on a determination that at least one of two points defined about the initial trained timing fails a two-point sampling.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Inventors: Venkatesh Prasad RAMACHANDRA, Jang Woo LEE, Srinivas RAJENDRA, Anil PAI
  • Publication number: 20230377677
    Abstract: Techniques for mitigating/eliminating the impact of duty distortion caused by delays in clock paths within a built-in high-frequency test circuit for NAND flash are disclosed. By mitigating or eliminating the impact of duty distortion, accuracy of the valid data window measurement is ensured. Rising edges of a strobe clock signal and an inverted strobe clock signal are used to respectively locate even and odd data (or vice versa) within an input buffer of the NAND flash during respective sweeps of the strobe and inverted strobe clock signals. In this manner, even if the strobe clock signal's duty ratio is distorted, there is no impact on the valid data window measurement. Further, read latency is used to introduce delay to a read enable (RE) clock signal, thereby obviating the need for a replica controlled delay in the RE clock path and eliminating the duty distortion that would otherwise occur.
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Inventors: HOON CHOI, Anil Pai, Venkatesh Prasad Ramachandra
  • Patent number: D1015226
    Type: Grant
    Filed: October 9, 2021
    Date of Patent: February 20, 2024
    Assignee: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Venkatesh Prasad Bangalore Srinivas, Pradeep Prabhakar Kamble, Venkat Raju Chintalapalli Patta