Patents by Inventor Venkatesh Ramamurthy
Venkatesh Ramamurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230315143Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: ApplicationFiled: June 5, 2023Publication date: October 5, 2023Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
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Patent number: 11703906Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: GrantFiled: November 5, 2021Date of Patent: July 18, 2023Assignee: Intel CorporationInventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
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Publication number: 20220129031Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: ApplicationFiled: November 5, 2021Publication date: April 28, 2022Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
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Patent number: 11169560Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: GrantFiled: February 24, 2017Date of Patent: November 9, 2021Assignee: Intel CorporationInventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris Macnamara, John J. Browne, Ripan Das
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Patent number: 11157064Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to send a power operation initiation indication to the accelerator device via the subset of the plurality of interconnects, the power operation initiation indication to indicate a power operation to be performed on one or more infrastructure devices, receive a response the accelerator device, the response to indicate to the processor that the accelerator is ready for the power operation, and ucause the power operation to be performed on the accelerator device, the power operation to enable or disable power for the one or more of the infrastructure devices.Type: GrantFiled: September 28, 2017Date of Patent: October 26, 2021Assignee: INTEL CORPORATIONInventors: Bharat S. Pillilli, Eswaramoorthi Nallusamy, Ramamurthy Krithivas, Vivek Garg, Venkatesh Ramamurthy
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Publication number: 20210318971Abstract: An example compute node is disclosed that includes a plurality of processor cores. The example further includes an operating system (OS) having an OS power management (OSPM) engine to determine that a first of the plurality of processor cores has entered an idle state; and a system management mode (SMM) handler to detect a system management interrupt (SMI) and transition control of hardware resources of the first processor core from the OS to a basic input output system (BIOS) to enter a system management mode (SMM) in order to perform one or more platform management operations.Type: ApplicationFiled: March 22, 2021Publication date: October 14, 2021Inventors: Gaurav Khanna, Prashant Sethi, Venkatesh Ramamurthy
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Patent number: 10956345Abstract: A method is described. The method includes determining that a first of a plurality of processor cores in a multi-processor computing system has entered an idle state, triggering a SMI for the first processor core, the first processor core entering a system management mode (SMM) and performing one or more platform management operations.Type: GrantFiled: April 1, 2016Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Gaurav Khanna, Prashant Sethi, Venkatesh Ramamurthy
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Patent number: 10592254Abstract: Technologies for fast low-power startup include a computing device with a processor having a power management integrated circuit. The computing device initializes platform components into a low-power state and determines, in a pre-boot firmware environment, the battery state of the computing device. The computing device determines a minimum-power startup (MPS) configuration that identifies platform components to be energized and determines whether the battery state is sufficient for the MPS configuration. If sufficient, the computing device energizes the platform components of the MPS configuration and boots into an MPS boot mode. In the MPS boot mode, the computing device may execute one or more user-configured application(s). If the battery state is sufficient for normal operation, the computing device may boot into a normal mode. In the normal mode, the user may configure the MPS configuration by selecting features for the future MPS boot mode. Other embodiments are described and claimed.Type: GrantFiled: September 5, 2017Date of Patent: March 17, 2020Assignee: Intel CorporationInventors: Rajesh Poornachandran, Vincent J. Zimmer, Karunakara Kotary, Venkatesh Ramamurthy, Pralhad M. Madhavi
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Publication number: 20190384348Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: ApplicationFiled: February 24, 2017Publication date: December 19, 2019Inventors: Vasudevan SRINIVASAN, Krishnakanth V. SISTLA, Corey D. GOUGH, Ian M. STEINER, Nikhil GUPTA, Vivek GARG, Ankush VARMA, Sujal A. VORA, David P. LERNER, Joseph M. SULLIVAN, Nagasubramanian GURUMOORTHY, William J. BOWHILL, Venkatesh RAMAMURTHY, Chris MACNAMARA, John J. BROWNE, Ripan DAS
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Patent number: 10373124Abstract: Technologies for generating tasks from communication messages includes a mobile computing device for monitoring communication messages, parsing the communication messages to detect content indicative of upcoming tasks, generating a task for each of the upcoming tasks detected, generating a task list from the generated tasks, and generating an alarm for each task. Additionally, the mobile computing device receives tasks generated by a cloud server.Type: GrantFiled: December 6, 2016Date of Patent: August 6, 2019Assignee: Intel CorporationInventors: Gyan Prakash, Nagasubramanian Gurumoorthy, Saurabh Dadu, Venkatesh Ramamurthy, Rama Sawhney
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Publication number: 20190094946Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to send a power operation initiation indication to the accelerator device via the subset of the plurality of interconnects, the power operation initiation indication to indicate a power operation to be performed on one or more infrastructure devices, receive a response the accelerator device, the response to indicate to the processor that the accelerator is ready for the power operation, and ucause the power operation to be performed on the accelerator device, the power operation to enable or disable power for the one or more of the infrastructure devices.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Applicant: INTEL CORPORATIONInventors: BHARAT S. PILLILLI, ESWARAMOORTHI NALLUSAMY, RAMAMURTHY KRITHIVAS, VIVEK GARG, VENKATESH RAMAMURTHY
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Publication number: 20180107490Abstract: Technologies for fast low-power startup include a computing device with a processor having a power management integrated circuit. The computing device initializes platform components into a low-power state and determines, in a pre-boot firmware environment, the battery state of the computing device. The computing device determines a minimum-power startup (MPS) configuration that identifies platform components to be energized and determines whether the battery state is sufficient for the MPS configuration. If sufficient, the computing device energizes the platform components of the MPS configuration and boots into an MPS boot mode. In the MPS boot mode, the computing device may execute one or more user-configured application(s). If the battery state is sufficient for normal operation, the computing device may boot into a normal mode. In the normal mode, the user may configure the MPS configuration by selecting features for the future MPS boot mode. Other embodiments are described and claimed.Type: ApplicationFiled: September 5, 2017Publication date: April 19, 2018Inventors: Rajesh Poornachandran, Vincent J. Zimmer, Karunakara Kotary, Venkatesh Ramamurthy, Pralhad M. Madhavi
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Patent number: 9817673Abstract: Technologies for fast low-power startup include a computing device with a processor having a power management integrated circuit. The computing device initializes platform components into a low-power state and determines, in a pre-boot firmware environment, the battery state of the computing device. The computing device determines a minimum-power startup (MPS) configuration that identifies platform components to be energized and determines whether the battery state is sufficient for the MPS configuration. If sufficient, the computing device energizes the platform components of the MPS configuration and boots into an MPS boot mode. In the MPS boot mode, the computing device may execute one or more user-configured application(s). If the battery state is sufficient for normal operation, the computing device may boot into a normal mode. In the normal mode, the user may configure the MPS configuration by selecting features for the future MPS boot mode. Other embodiments are described and claimed.Type: GrantFiled: March 3, 2015Date of Patent: November 14, 2017Assignee: Intel CorporationInventors: Rajesh Poornachandran, Vincent J. Zimmer, Karunakara Kotary, Venkatesh Ramamurthy, Pralhad M. Madhavi
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Publication number: 20170286334Abstract: A method is described. The method includes determining that a first of a plurality of processor cores in a multi-processor computing system has entered an idle state, triggering a SMI for the first processor core, the first processor core entering a system management mode (SMM) and performing one or more platform management operations.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Gaurav Khanna, Prashant Sethi, Venkatesh Ramamurthy
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Publication number: 20170185128Abstract: An electronic device may be provided that includes logic, at least a portion which is hardware, to receive a plurality of transition requests within a configurable moving time period and to block a clock signal to one or more of the plurality of cores based on the received transition requests.Type: ApplicationFiled: December 24, 2015Publication date: June 29, 2017Inventors: Venkatesh Ramamurthy, Ripan Das
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Publication number: 20170083876Abstract: Technologies for generating tasks from communication messages includes a mobile computing device for monitoring communication messages, parsing the communication messages to detect content indicative of upcoming tasks, generating a task for each of the upcoming tasks detected, generating a task list from the generated tasks, and generating an alarm for each task. Additionally, the mobile computing device receives tasks generated by a cloud server.Type: ApplicationFiled: December 6, 2016Publication date: March 23, 2017Inventors: Gyan Prakash, Nagasubramanian Gurumoorthly, Saurabh Dadu, Venkatesh Ramamurthy, Rama Sawhney
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Patent number: 9596085Abstract: An embodiment includes a method executed by at least one processor comprising: an out-of-band cryptoprocessor receiving security credentials from a battery, which is included in a mobile computing node that comprises the at least one processor, while the mobile computing node is engaged in at least one of (a) booting, and (b) exchanging the battery after booting and during run-time; the cryptoprocessor accessing an authentication key; and the cryptoprocessor successfully authenticating the battery, via out-of-band processing, based on the security credentials and the authentication key. In an embodiment the security credentials are included in a certificate. Other embodiments are described herein.Type: GrantFiled: June 13, 2013Date of Patent: March 14, 2017Assignee: Intel CorporationInventors: Gyan Prakash, Venkatesh Ramamurthy, Rajesh Poornachandran, Hong Li, Jesse Walker
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Patent number: 9530027Abstract: Generally, this disclosure describes providing theft deterrence for a device while in transit. The system may include lock state circuitry configured to receive and store an unlock token, the unlock token configured to indicate that an associated device has successfully completed transit from a source to a destination; and lock state read circuitry configured to request the unlock token from the lock state circuitry and to determine whether the associated device has successfully completed transit from the source to the destination based on the unlock token.Type: GrantFiled: May 11, 2012Date of Patent: December 27, 2016Assignee: Intel CorporationInventors: Shahrokh Shahidzadeh, Venkatesh Ramamurthy, Reinhard R. Steffens, Gyan Prakash, Stephen L. Smith, Christian Von Reventlow, Farzad Esfandiari
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Patent number: 9514448Abstract: Technologies for generating tasks from communication messages includes a mobile computing device for monitoring communication messages, parsing the communication messages to detect content indicative of upcoming tasks, generating a task for each of the upcoming tasks detected, generating a task list from the generated tasks, and generating an alarm for each task. Additionally, the mobile computing device receives tasks generated by a cloud server.Type: GrantFiled: December 28, 2012Date of Patent: December 6, 2016Assignee: Intel CorporationInventors: Gyan Prakash, Nagasubramanian Gurumoorthly, Saurabh Dadu, Venkatesh Ramamurthy, Rama Sawhney
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Publication number: 20160259649Abstract: Technologies for fast low-power startup include a computing device with a processor having a power management integrated circuit. The computing device initializes platform components into a low-power state and determines, in a pre-boot firmware environment, the battery state of the computing device. The computing device determines a minimum-power startup (MPS) configuration that identifies platform components to be energized and determines whether the battery state is sufficient for the MPS configuration. If sufficient, the computing device energizes the platform components of the MPS configuration and boots into an MPS boot mode. In the MPS boot mode, the computing device may execute one or more user-configured application(s). If the battery state is sufficient for normal operation, the computing device may boot into a normal mode. In the normal mode, the user may configure the MPS configuration by selecting features for the future MPS boot mode. Other embodiments are described and claimed.Type: ApplicationFiled: March 3, 2015Publication date: September 8, 2016Inventors: Rajesh Poornachandran, Vincent J. Zimmer, Karunakara Kotary, Venkatesh Ramamurthy, Pralhad M. Madhavi