Patents by Inventor Venkatesh Ramamurthy

Venkatesh Ramamurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12332871
    Abstract: Techniques are provided for maintaining snapshots of state information for a plurality of resource entities, within a distributed cloud service. A first snapshot of state information for the plurality of resource entities is maintained at an endpoint in persistent storage. A request to modify resources allocated to resource entities is received. A virtual lock on the state information reflected in the first snapshot is obtained. Upon obtaining the virtual lock, a service determines, based on the first snapshot, that there are available resources to perform the request to modify resources. A second snapshot of the state information, reflecting the modification of resources allocated to resource entities, is then generated and stored at the endpoint in persistent storage. The virtual lock on the state information is released and the resources allocated to the resource entities are modified according to the request.
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: June 17, 2025
    Assignee: Oracle International Corporation
    Inventors: Nagarajan Muthukrishnan, Prasanna Venkatesh Ramamurthi, Ranjit Murali, Srikanth Nagandla
  • Publication number: 20250021542
    Abstract: Techniques are provided for maintaining snapshots of state information for a plurality of resource entities, within a distributed cloud service. A first snapshot of state information for the plurality of resource entities is maintained at an endpoint in persistent storage. A request to modify resources allocated to resource entities is received. A virtual lock on the state information reflected in the first snapshot is obtained. Upon obtaining the virtual lock, a service determines, based on the first snapshot, that there are available resources to perform the request to modify resources. A second snapshot of the state information, reflecting the modification of resources allocated to resource entities, is then generated and stored at the endpoint in persistent storage. The virtual lock on the state information is released and the resources allocated to the resource entities are modified according to the request.
    Type: Application
    Filed: July 11, 2023
    Publication date: January 16, 2025
    Inventors: Nagarajan Muthukrishnan, Prasanna Venkatesh Ramamurthi, Ranjit Murali, Srikanth Nagandla
  • Publication number: 20250004495
    Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
    Type: Application
    Filed: July 5, 2024
    Publication date: January 2, 2025
    Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
  • Publication number: 20240403157
    Abstract: Systems and techniques for live memory recovery using a pluggable memory module are described herein. It may be detected that a spare memory module has been inserted into a computing device based on a signal transmitted from the spare memory module. The spare memory module may be initialized. A dynamic random-access memory (DRAM) module of the computing device may be identified that is predicted to fail. Freeze instructions may be transmitted to a virtual machine manager to pause virtual machines executing on the computing device. Memory data may be transferred from the DRAM module to the spare memory module. Memory addresses may be remapped from the DRAM module to the spare memory module. Unfreeze instructions may be transmitted to the virtual machine manager to resume the virtual machines executing on the computing device.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 5, 2024
    Inventors: Karunakara Kotary, Ankur Garg, Venkatesh Ramamurthy, Nagasubramanian Gurumoorthy
  • Patent number: 12066853
    Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: August 20, 2024
    Assignee: Intel Corporation
    Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
  • Publication number: 20230315143
    Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 5, 2023
    Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
  • Patent number: 11703906
    Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
  • Patent number: 11392388
    Abstract: Provided is a process for determining a number of parallel threads for a request. The process involves receiving availability data regarding processing resources, wherein the availability data indicates which processing resources are idle or are to become idle. Based on the availability data, a number of parallel threads for the request is determined.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: July 19, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mahesh Kumar Behera, Prasanna Venkatesh Ramamurthi, Antoni Wolski
  • Publication number: 20220129031
    Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
    Type: Application
    Filed: November 5, 2021
    Publication date: April 28, 2022
    Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
  • Patent number: 11169560
    Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris Macnamara, John J. Browne, Ripan Das
  • Patent number: 11157064
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to send a power operation initiation indication to the accelerator device via the subset of the plurality of interconnects, the power operation initiation indication to indicate a power operation to be performed on one or more infrastructure devices, receive a response the accelerator device, the response to indicate to the processor that the accelerator is ready for the power operation, and ucause the power operation to be performed on the accelerator device, the power operation to enable or disable power for the one or more of the infrastructure devices.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: October 26, 2021
    Assignee: INTEL CORPORATION
    Inventors: Bharat S. Pillilli, Eswaramoorthi Nallusamy, Ramamurthy Krithivas, Vivek Garg, Venkatesh Ramamurthy
  • Patent number: 11150996
    Abstract: A method, a master database node and a subscriber database node for optimizing an index. The method for optimizing index includes: checking, by a master database node, if role information of an index matches role information of the master database node, when the index is added into the master database node; updating database information by using the index when the role information of the index matches the role information of the master database node. In this invention, unnecessary indexes in the master database node and the subscriber database node are reduced while keeping the schema the same. Furthermore, unnecessary logs transmitted from the master database node to the subscriber database node are reduced.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: October 19, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Prasanna Venkatesh Ramamurthi, Vamsi Krishna, Mahesh Kumar Behera
  • Publication number: 20210318971
    Abstract: An example compute node is disclosed that includes a plurality of processor cores. The example further includes an operating system (OS) having an OS power management (OSPM) engine to determine that a first of the plurality of processor cores has entered an idle state; and a system management mode (SMM) handler to detect a system management interrupt (SMI) and transition control of hardware resources of the first processor core from the OS to a basic input output system (BIOS) to enter a system management mode (SMM) in order to perform one or more platform management operations.
    Type: Application
    Filed: March 22, 2021
    Publication date: October 14, 2021
    Inventors: Gaurav Khanna, Prashant Sethi, Venkatesh Ramamurthy
  • Patent number: 11068499
    Abstract: Method, device, and system for peer-to-peer data replication are provided. The method includes: generating a first commit redo record attached with a CSN when a first write operation happens on a first physical entity in a master node, wherein the master node is preset with the first physical entity and a second physical entity and is connected to a first subscriber node and a second subscriber node; pushing, the first commit redo record to a first subscriber node corresponding to the first physical entity based on mapping relationships between the physical entities and the subscriber nodes, wherein the first commit redo record is used for replicating data of the first write operation from the master node to the first subscriber node, and then to the second subscriber node through pushing, by the first subscriber node, the received first commit redo record to the second subscriber node.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: July 20, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Prasanna Venkatesh Ramamurthi, Vamsi Krishna
  • Patent number: 10956345
    Abstract: A method is described. The method includes determining that a first of a plurality of processor cores in a multi-processor computing system has entered an idle state, triggering a SMI for the first processor core, the first processor core entering a system management mode (SMM) and performing one or more platform management operations.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Gaurav Khanna, Prashant Sethi, Venkatesh Ramamurthy
  • Publication number: 20200097297
    Abstract: Provided is a process for determining a number of parallel threads for a request. The process involves receiving availability data regarding processing resources, wherein the availability data indicates which processing resources are idle or are to become idle. Based on the availability data, a number of parallel threads for the request is determined.
    Type: Application
    Filed: November 27, 2019
    Publication date: March 26, 2020
    Inventors: Mahesh Kumar BEHERA, Prasanna Venkatesh RAMAMURTHI, Antoni WOLSKI
  • Patent number: 10592254
    Abstract: Technologies for fast low-power startup include a computing device with a processor having a power management integrated circuit. The computing device initializes platform components into a low-power state and determines, in a pre-boot firmware environment, the battery state of the computing device. The computing device determines a minimum-power startup (MPS) configuration that identifies platform components to be energized and determines whether the battery state is sufficient for the MPS configuration. If sufficient, the computing device energizes the platform components of the MPS configuration and boots into an MPS boot mode. In the MPS boot mode, the computing device may execute one or more user-configured application(s). If the battery state is sufficient for normal operation, the computing device may boot into a normal mode. In the normal mode, the user may configure the MPS configuration by selecting features for the future MPS boot mode. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Rajesh Poornachandran, Vincent J. Zimmer, Karunakara Kotary, Venkatesh Ramamurthy, Pralhad M. Madhavi
  • Publication number: 20190243717
    Abstract: A method, a master database node and a subscriber database node for optimizing index. The method for optimizing index includes: checking, by a master database node, if role information of an index matches role information of the master database node, when the index is added into the master database node; updating database information by using the index when the role information of the index matches the role information of the master database node. In this invention, unnecessary indexes in the master database node and the subscriber database node are reduced while keeping the schema the same. Furthermore, unnecessary logs transmitted from the master database node to the subscriber database node are reduced.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Prasanna Venkatesh RAMAMURTHI, Vamsi KRISHNA, Mahesh Kumar BEHERA
  • Patent number: 10373124
    Abstract: Technologies for generating tasks from communication messages includes a mobile computing device for monitoring communication messages, parsing the communication messages to detect content indicative of upcoming tasks, generating a task for each of the upcoming tasks detected, generating a task list from the generated tasks, and generating an alarm for each task. Additionally, the mobile computing device receives tasks generated by a cloud server.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Gyan Prakash, Nagasubramanian Gurumoorthy, Saurabh Dadu, Venkatesh Ramamurthy, Rama Sawhney
  • Patent number: 10303552
    Abstract: A method, a master database node and a subscriber database node for optimizing index. The method for optimizing index includes: checking, by a master database node, if role information of an index matches role information of the master database node, when the index is added into the master database node; updating database information by using the index when the role information of the index matches the role information of the master database node. In this invention, unnecessary indexes in the master database node and the subscriber database node are reduced while keeping the schema the same. Furthermore, unnecessary logs transmitted from the master database node to the subscriber database node are reduced.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: May 28, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Prasanna Venkatesh Ramamurthi, Vamsi Krishna, Mahesh Kumar Behera