Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.

Abstract: Apparatuses and methods of pulse shaping a pulse signal for programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cell are described. In one method a pulse shape of a pulse signal is controlled to include four or more phases for programming or erasing a SONOS memory cell. A write cycle is performed to program or erase the SONOS memory with the pulse signal with the four or more phases.

Abstract: A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and a second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.

Abstract: A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement. The volatile portion includes cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage (VPWR) and the first output node, and the second FET coupled between VPWR and the second output node. A gate of the first FET is coupled to the second output node, and a gate of the second FET is coupled to the first output node.

Abstract: A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.

Abstract: A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.

Abstract: Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and a second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.

Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.

Abstract: A method of making a semiconductor device is provided. The method includes forming a deep well (DWELL) and a well (WELL) in a first region of a substrate, the WELL adjacent a surface of the substrate so that an interface between the WELL and DWELL is exposed on the surface of the substrate. A channel for a DEMOS transistor is formed in the first region over the interface and includes a first channel formed in the WELL and a second channel formed in the DWELL. A gate layer is deposited and patterned to concurrently form in the first region a first gate for the DEMOS transistor and in a second region a second gate for an ESD device. Dopants are implanted in the first and second regions to concurrently form a drain extension of the DEMOS transistor, and an ESD diffusion region of the ESD device.

Abstract: A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement. The volatile portion includes cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage (VPWR) and the first output node, and the second FET coupled between VPWR and the second output node. A gate of the first FET is coupled to the second output node, and a gate of the second FET is coupled to the first output node.

Abstract: Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM) over a substrate including a first-SONOS region and a second-SONOS region. A first tunnel mask (TUNM) is formed over the HM exposing a first portion of the HM in the second-SONOS region. The first portion of the HM is etched, a channel for a first SONOS device implanted through a first pad oxide overlying the second-SONOS region and the first TUNM removed. A second TUNM is formed exposing a second portion of the HM in the first-SONOS region. The second portion of the HM is etched, a channel for a second SONOS device implanted through a second pad oxide overlying the first-SONOS region and the second TUNM removed. The first and second pad oxides are concurrently etched, and the HM removed.

Abstract: Apparatuses and methods of pulse shaping a pulse signal for programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cell are described. In one method a pulse shape of a pulse signal is controlled to include four or more phases for programming or erasing a SONOS memory cell. A write cycle is performed to program or erase the SONOS memory with the pulse signal with the four or more phases.

Abstract: A memory device that includes a non-volatile memory (NVM) transistor which has an indium doped channel and a gate stack overlying the channel formed in a first region of a substrate and a metal-oxide-semiconductor (MOS) transistor formed in a second region of the substrate in which the gate oxide of the MOS and the oxide layer of the NVM transistor are formed concurrently.

Abstract: A memory structure including a memory array of a plurality of memory cells arranged in rows and columns, the plurality of memory cells including a pair of adjacent memory cells in a row of the memory array, wherein the pair of adjacent memory cells include a single, shared source-line through which each of the memory cells in the pair of adjacent memory cells is coupled to a voltage source. Methods of operating a memory including the memory structure are also described.