Abstract: A “weak” undriven state is defined as a signal state, distinguished from conventional unknown and high impedance states, and methods of representing this “weak” undriven state in circuit modelling and power aware digital/mixed-signal simulations for comprehensive and complete RTL-level design verification. The conventional unknown state refers to a circuit element that is powered but has an unknown value, a circuit element that is not powered, or a circuit element having an undriven, floating signal. The unknown state is modified, and the “weak” undriven state refers to a circuit element that is not powered and has an unknown value. The “weak” undriven state can have an electrically high impedance to known supply or ground when no other circuit element is active. The “weak” undriven state distinction is particularly useful to model and verify circuit designs known to be resilient to “weak” undriven states, using event driven logic circuit simulators.

Abstract: A method for boundary port modelling that correctly handles back-to-back isolation intent, level shifter intent and voltage level association, by providing hard association of power domains to soft data objects, such as wires. The method includes identifying a boundary port in a detailed power intent (DPI) for a soft design object (SDO). A non-wire object is inserted in the SDO for the boundary port. In the DPI, a power domain of the boundary port is assigned to the non-wire object.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

Abstract: A method includes obtaining, by a computer processor according to computer instructions, data models of intellectual property (IP) cores for hierarchical clock domain crossing (CDC) and reset domain crossing (RDC) verification, where the IP cores include reusable units of logic for a system on a chip (SoC), and performing, by the computer processor based on the data models of the IP cores, the hierarchical CDC and RDC verification for the SoC according to integration of the IP cores in the SoC, where the hierarchical CDC and RDC verification includes consistency verification of functional assumptions with structural analysis of the IP cores individually and in a context of use in the SoC.

Abstract: A technique for convergence verification including receiving a data object representation of a first circuit block, receiving one or more assumptions associated with the first circuit block, identifying a synchronization scheme coupled to a port of the first circuit block, determining that the synchronization scheme is within a threshold flip-flop depth, identifying, based on the determination that the synchronization scheme is within the threshold flip-flop depth, a type of the synchronization scheme and a flip-flop depth between the synchronization scheme and the port, generating first convergence information for the first circuit block based on the identified type and flip-flop depth of the synchronization scheme, and outputting the generated convergence information.

Abstract: A method for timing analysis includes receiving a physical design of an electric circuit, selecting a timing path within the electric circuit, and determining that the selected timing path includes a first logic cell implemented with a first type of transistor and a second logic cell implemented with a second type of transistor. The method further includes running a set of process corners with the first type of transistor at a given corner and the second type of transistor at a condition other than the given corner. The first type of transistor has a delay that is based on process correlation with the second type of transistor. The method also includes determining whether a timing requirement is met or not met for the selected timing path, and then reporting whether the timing requirement is met or not met.

Abstract: A technique for domain crossing verification including receiving a first data object representation of an electrical circuit, performing a domain crossing check on the first data object representation to identify a domain crossing issue, receiving an indication of an assumption for the identified domain crossing issue, converting the first data object representation of the electrical circuit to a second data object representation of the electrical circuit, wherein the second data object representation is synthesized based on the first data object representation, determining one or more verification checks based on the second data object representation and the assumption for the identified domain crossing issue, and performing the one or more verification checks on the second data object representation of the electrical circuit.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

Abstract: A method comprises creating an electronic module design having a plurality of electronic components and defining a model of functional behavior of a subset of the plurality of electronic components, the subset of the plurality of electronic components excluding a first electronic component. Functional behavior of the first electronic component is defined in a user-defined functional design intent file based on a first template, and a power behavior of the first electronic component is defined in a user-defined power design intent file based on a second template. A simulation file is generated based on the model of functional behavior and based on the functional behavior and the power behavior of the first electronic component. The simulation file is run to simulate operation of the electronic module design. A performance status is determined of the electronic module design in response to running the simulation file.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

Abstract: A method comprises creating an electronic module design having a plurality of electronic components and defining a model of functional behavior of a subset of the plurality of electronic components, the subset of the plurality of electronic components excluding a first electronic component. Functional behavior of the first electronic component is defined in a user-defined functional design intent file based on a first template, and a power behavior of the first electronic component is defined in a user-defined power design intent file based on a second template. A simulation file is generated based on the model of functional behavior and based on the functional behavior and the power behavior of the first electronic component. The simulation file is run to simulate operation of the electronic module design. A performance status is determined of the electronic module design in response to running the simulation file.

Abstract: A method for boundary port modelling that correctly handles back-to-back isolation intent, level shifter intent and voltage level association, by providing hard association of power domains to soft data objects, such as wires. The method includes identifying a boundary port in a detailed power intent (DPI) for a soft design object (SDO). A non-wire object is inserted in the SDO for the boundary port. In the DPI, a power domain of the boundary port is assigned to the non-wire object.

Abstract: Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to leakage and dynamic power. This invention is a technique for clock gate optimization to aid the clock tree synthesis. The technique enables cloning and redistribution of the fanout among the existing equivalent clock gates. The technique is placement aware and hence reduces overall clock wire length and area. The technique involves employing the k-means clustering algorithm to geographically partition the design's registers. This invention improves the clock tree synthesis quality on a complex design.

Abstract: Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to leakage and dynamic power. This invention is a technique for clock gate optimization to aid the clock tree synthesis. The technique enables cloning and redistribution of the fanout among the existing equivalent clock gates. The technique is placement aware and hence reduces overall clock wire length and area. The technique involves employing the k-means clustering algorithm to geographically partition the design's registers. This invention improves the clock tree synthesis quality on a complex design.

Abstract: An aspect of the present invention selects a maximum voltage and a minimum voltage in respective sub-intervals of a timing window in which an output of a cell is expected to switch, and performing timing analysis based on the selected maximum voltage and the selected minimum voltage. By using appropriate smaller sub-intervals within the timing window, more optimal physical layout of the design may be obtained. In an embodiment, the sub-intervals equal a cell delay, i.e., a delay between an input change to an output change for a corresponding cell. According to another aspect of the present invention, the sub-interval for later cells in a timing path are modified based on a modified timing window of previous cells in the timing path, to reduce the computational requirement.

Abstract: An aspect of the present invention provides for timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy. In an embodiment, an optimized model for a circuit block is created by combining information provided by two different models of the same circuit block and performing timing analysis based on the optimized model. In an embodiment, the two models correspond to black box and interface timing models. In the optimized model, ports for which only timing arc information is deemed necessary are modeled using corresponding information from the black box model, while ports for which more accurate or detailed information is deemed necessary are modeled using corresponding information from the interface timing model. The optimized model enables the integration to be performed with a balance of resource requirements and accuracy.

Abstract: The invention provides an X-ray crystal structure of the 30S ribosome, obtained from Thermus thermophilus 30S subunit, having a tetragonal space group P41212 with unit cell dimensions of a=401.4±4.0 ?, b=401.4±4.0 ?, c=175.9±5.0 ?. An advantageous feature of the structure is that it diffracts beyond 3 ? resolution. The invention also provides a crystal of 30S having the three dimensional atomic coordinates of the 30S ribosome, the coordinates being provided in Tables 1A and 1B. The data may be used for the rational design and modelling of inhibitors for the 30S ribosome, which have potential use as antibiotics.

Abstract: An aspect of the present invention provides for timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy. In an embodiment, an optimized model for a circuit block is created by combining information provided by two different models of the same circuit block and performing timing analysis based on the optimized model. In an embodiment, the two models correspond to black box and interface timing models. In the optimized model, ports for which only timing arc information is deemed necessary are modeled using corresponding information from the black box model, while ports for which more accurate or detailed information is deemed necessary are modeled using corresponding information from the interface timing model. The optimized model enables the integration to be performed with a balance of resource requirements and accuracy.

Abstract: An aspect of the present invention selects a maximum voltage and a minimum voltage in respective sub-intervals of a timing window in which the output of a cell is expected to switch, and performing timing analysis based on the selected values. By using appropriate smaller sub-intervals within the timing window, more optimal physical layout of the design may be obtained. In an embodiment, the sub-intervals equal a cell delay, i.e., the delay between an input change to an output change for the corresponding cell. According to another aspect of the present invention, the sub-interval for later cells in a timing path are modified based on modified timing window of previous cells in the path, to reduce the computational requirement.