Patents by Inventor Venugopal Boynapalli
Venugopal Boynapalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9806717Abstract: Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.Type: GrantFiled: October 10, 2016Date of Patent: October 31, 2017Assignee: QUALCOMM IncorporatedInventors: Kevin Robert Bowles, Jose Gabriel Corona, Venugopal Boynapalli
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Publication number: 20170287933Abstract: A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.Type: ApplicationFiled: September 13, 2016Publication date: October 5, 2017Inventors: Xiangdong CHEN, Venugopal BOYNAPALLI, Satyanarayana SAHU, Hyeokjin LIM, Mukul GUPTA
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Publication number: 20170257080Abstract: In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.Type: ApplicationFiled: March 4, 2016Publication date: September 7, 2017Inventors: Seid Hadi RASOULI, Xiangdong CHEN, Venugopal BOYNAPALLI
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Patent number: 9755618Abstract: In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.Type: GrantFiled: March 4, 2016Date of Patent: September 5, 2017Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Xiangdong Chen, Venugopal Boynapalli
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Publication number: 20170237434Abstract: The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.Type: ApplicationFiled: February 16, 2016Publication date: August 17, 2017Inventors: Qi YE, Animesh DATTA, Venkatasubramanian NARAYANAN, Venugopal BOYNAPALLI
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Patent number: 9666301Abstract: An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit.Type: GrantFiled: September 16, 2014Date of Patent: May 30, 2017Assignee: QUALCOMM IncorporatedInventors: Venugopal Boynapalli, Kashyap Ramachandra Bellur, Prabaharan Balu, Bilal Zafar, Alex Dongkyu Park, Sei Seung Yoon
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Patent number: 9577639Abstract: A MOS device includes a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate. The MOS device also includes a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate. The second MOS transistor source and the first MOS transistor source are coupled to a first voltage source. The MOS device includes a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the third MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source being coupled to the first MOS transistor source, the third MOS transistor drain being coupled to the second MOS transistor source, the third MOS transistor gate floating.Type: GrantFiled: September 24, 2015Date of Patent: February 21, 2017Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Bruce Lim, Mukul Gupta, Hananel Kang, Chih-lung Kao, Radhika Guttal
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Publication number: 20170026044Abstract: Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.Type: ApplicationFiled: October 10, 2016Publication date: January 26, 2017Inventors: Kevin Robert Bowles, Jose Gabriel Corona, Venugopal Boynapalli
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Patent number: 9490813Abstract: Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.Type: GrantFiled: November 6, 2014Date of Patent: November 8, 2016Assignee: QUALCOMM IncorporatedInventors: Kevin Robert Bowles, Jose Gabriel Corona, Venugopal Boynapalli
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Publication number: 20160134286Abstract: Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.Type: ApplicationFiled: November 6, 2014Publication date: May 12, 2016Inventors: Kevin Robert Bowles, Jose Gabriel Corona, Venugopal Boynapalli
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Publication number: 20160078965Abstract: An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit.Type: ApplicationFiled: September 16, 2014Publication date: March 17, 2016Inventors: Venugopal Boynapalli, Kashyap Ramachandra Bellur, Prabaharan Balu, Bilal Zafar, Alex Dongkyu Park, Sei Seung Yoon
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Publication number: 20160004617Abstract: An instruction cell array is provided that comprises an array of tiles. Each tile includes a set of input/output (I/O) ports for switching between a plurality of input channels and a plurality of corresponding output channels. In addition, each tile includes an instruction cell comprising a plurality of dedicated logic gates for producing an instruction cell output from selected ones of the tile's input channels. Each I/O port is configured to select from the tile's instruction cell output and from the input channels for the remaining I/O ports for the tile to form the I/O port's output channels. To prevent combinatorial loops during an automatic test pattern generation (ATPG) of the array, the instruction cell array disclosed herein is configured in the testing mode such at least a subset of the I/O ports for each tile prevent any of their output channels from being formed as combinatorial signals.Type: ApplicationFiled: July 3, 2014Publication date: January 7, 2016Inventors: Hari Madhava Rao, Joseph Weizhou Fang, Sami Khawam, Ioannis Nousias, Raju Macha, Ihab Abdelmuti, Venugopal Boynapalli
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Patent number: 9230691Abstract: A cross-bar switch is provided that enables each master from a plurality of masters to read from and write to selected memories from an array of memories. A logic circuit controls the cross-bar switch so that redundancy for the memories is provided by a shared redundancy storage element.Type: GrantFiled: November 6, 2014Date of Patent: January 5, 2016Assignee: QUALCOMM IncorporatedInventors: Venugopal Boynapalli, Bilal Zafar
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Patent number: 9189438Abstract: Various aspects of dynamic power reduction in a bus communication architecture are described herein as embodied in an XBAR architecture that provides flexible gating of multiple paths and repeater circuitry to allow any of a number of selected clients to communicate with any of the other interconnected clients while reducing dynamic power consumption by disabling unused repeater circuitry in the bus communication architecture.Type: GrantFiled: March 13, 2013Date of Patent: November 17, 2015Assignee: QUALCOMM IncorporatedInventors: Hari Rao, Venugopal Boynapalli, Kevin Robert Bowles, Vijay Bantval
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Patent number: 9081060Abstract: A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.Type: GrantFiled: October 4, 2013Date of Patent: July 14, 2015Assignee: QUALCOMM IncorporatedInventors: Hari Rao, Venkatasubramanian Narayanan, Venugopal Boynapalli, Sagar Suresh Sabade, Bilal Zafar
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Patent number: 9071239Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.Type: GrantFiled: March 13, 2013Date of Patent: June 30, 2015Assignee: QUALCOMM IncorporatedInventors: Chulmin Jung, Sei Seung Yoon, Esin Terzioglu, Hari Ananthanarayanan, Venugopal Boynapalli
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Publication number: 20150100842Abstract: A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.Type: ApplicationFiled: October 4, 2013Publication date: April 9, 2015Applicant: QUALCOMM IncorporatedInventors: Hari Rao, Venkatasubramanian Narayanan, Venugopal Boynapalli, Sagar Suresh Sabade, Bilal Zafar
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Patent number: 8860493Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.Type: GrantFiled: March 13, 2013Date of Patent: October 14, 2014Assignee: QUALCOMM IncorporatedInventors: Chulmin Jung, Sei Seung Yoon, Esin Terzioglu, Hari Ananthanarayanan, Venugopal Boynapalli
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Publication number: 20140266398Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: QUALCOMM IncorporatedInventors: Chulmin Jung, Sei Seung Yoon, Esin Terzioglu, Hari Ananthanarayanan, Venugopal Boynapalli
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Publication number: 20140281112Abstract: Various aspects of dynamic power reduction in a bus communication architecture are described herein as embodied in an XBAR architecture that provides flexible gating of multiple paths and repeater circuitry to allow any of a number of selected clients to communicate with any of the other interconnected clients while reducing dynamic power consumption by disabling unused repeater circuitry in the bus communication architecture.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: QUALCOMM IncorporatedInventors: Hari Rao, Venugopal Boynapalli, Kevin Robert Bowles, Vijay Bantval