Abstract: A low power interconnect allows client to client communication using an XBAR architecture. An XBAR compiler generates chip designs with XBAR data paths structured to reduce energy consumption and delay. Repeaters inserted into XBAR data paths reduce resistance capacitance (RC) delays so that a design can support desired frequency specifications along a path. Dynamic power consumption is reduced by inserting latch repeaters in the XBAR track. The latch repeaters each include a transmission gate and a latch. Select circuitry couples selected clients to a path. Enable circuitry opens the transmission gates located on the path between the selected clients. Latch repeaters that are not enabled on a given communication cycle gate off the unused portions of the path and maintain the data that was latched on a previous cycle.

Abstract: In an embodiment, a method of testing an error correction scheme includes selectively observing and controlling data at one or more intermediate test points within an error correction circuit. Erroneous data may be selectively injected at a first intermediate test point and data related to the erroneous data may be observed at a second intermediate test point.