Abstract: Systems and methods are provided for replacing a first server of a first node a computer network by adding a second server configured with a database system as a second node to the computer network. A snapshot of a first database of database files that is communicatively coupled to the first node may be taken. The snapshot may be applied to the second server by attaching the snapshot of the first database as a second database to the second server and configuring the second server to match the first server. A failover of the computer network to the second node with the second server having the second database attached may be forced. Voting may be switched to the second server of the second node of the computer network and the first node of the computer network may be removed when the forced failover is successful.

Abstract: A tissue lumen stent is provided with a body having an elongated tubular configuration and a foreshortened configuration. In the foreshortened configuration, downstream and upstream ends of the body expand radially into downstream and upstream flange structures, leaving a generally cylindrical saddle region therebetween. In some embodiments, the flange structures are non-symmetrical with respect to one another. Systems and methods of using the stents are also disclosed.

Abstract: Described herein are methods, systems, and pharmaceutical compositions for using Trigonelline (TRG), an alkaloid found in the seeds of many plants, including coffee beans, to attenuate Spike-protein exacerbated lipotoxicity and mitochondria stress in endothelial cells and cardiomyocytes to protect the heart from injuries caused by SARS-CoV-2 Spike protein under obesity.

Abstract: Described herein are methods and systems using ADAM30 as a biomarker to help early diagnosis of congenital malformed vasculatures in children and which can also serve as a companion diagnostic biomarker for malformed vasculatures, as well as a subpopulation of cancer cells, wherein blockage of activity of ADAM30 by a neutralized antibody or inhibitor can be used as a treatment strategy for those ADAM30-positive vascular endothelial cells and cancer cells.

Abstract: Described herein are methods and systems using ADAM30 as a biomarker to help early diagnosis of congenital malformed vasculatures in children and which can also serve as a companion diagnostic biomarker for malformed vasculatures, as well as a subpopulation of cancer cells, wherein blockage of activity of ADAM30 by a neutralized antibody or inhibitor can be used as a treatment strategy for those ADAM30-positive vascular endothelial cells and cancer cells.

Abstract: A method and a system for rating entities of a group is provided. Rating values for one or more other entities are received. The received rating values include a time stamp. A matrix of combined rating values is built, and entropy values for each entity are determined. The entropy value is indicative of a rate an entity rates other entities with a same rating value. Goodness values are determined for each entity. Each of the goodness values is dependent from a respective fairness value for each entity and the respective entropy value of each entity. The goodness value are indicative of a quality metric. The fairness values for each entity is determined. The fairness value is dependent on the related goodness value, the fairness value being indicative of a difference of an entity rating in comparison to other ratings. The determination of the goodness and fairness values are repeated until convergence.

Abstract: Disclosed includes a memory device and a method of operating the memory device. A voltage is applied to a word line coupled to first memory transistors of a first plurality of strings of transistors and second memory transistors of a second plurality of strings of transistors. A current flow through one or more of the first plurality of strings of transistors is enabled, while applying the voltage to the word line. A current flow through the second plurality of strings of transistors is disabled by floating source terminals and drain terminals of the second memory transistors, while enabling the current flow through the one or more of the first plurality of strings of transistors.

Abstract: This disclosure provides techniques for reducing leakage current in a non-volatile memory that does not include a local interconnect. In one example, a low-voltage pulse can be applied to all of the word-lines in all of the blocks of the non-volatile memory. The low-voltage pulse can be applied during a period in which the row decoder is typically idle in order to reduce the total amount of time required to program the non-volatile memory. After the conclusion low-voltage pulse, a global control line voltage can be applied at about the same level as the low-voltage pulse to keep the word-lines floating when the pulse is no longer applied.

Abstract: Disclosed includes a memory device and a method of operating the memory device. A voltage is applied to a word line coupled to first memory transistors of a first plurality of strings of transistors and second memory transistors of a second plurality of strings of transistors. A current flow through one or more of the first plurality of strings of transistors is enabled, while applying the voltage to the word line. A current flow through the second plurality of strings of transistors is disabled by floating source terminals and drain terminals of the second memory transistors, while enabling the current flow through the one or more of the first plurality of strings of transistors.

Abstract: This disclosure provides techniques for reducing leakage current in a non-volatile memory that does not include a local interconnect. In one example, a low-voltage pulse can be applied to all of the word-lines in all of the blocks of the non-volatile memory. The low-voltage pulse can be applied during a period in which the row decoder is typically idle in order to reduce the total amount of time required to program the non-volatile memory. After the conclusion low-voltage pulse, a global control line voltage can be applied at about the same level as the low-voltage pulse to keep the word-lines floating when the pulse is no longer applied.

Abstract: Methods for controlling a ramp rate of an output voltage derived from one or more charge pumps and reducing variation in the ramp rate due to process, voltage, and temperature (PVT) variations are described. In some embodiments, the ramp rate of the output voltage from one or more charge pumps may be controlled using a ramp rate control circuit that uses a digital counter to adjust (or step up) the output voltage from the one or more charge pumps based on a ramp rate schedule. The ramp rate schedule may specify varying output voltage levels for the one or more charge pumps during a time period in which the output voltage charges up from a first voltage to a second voltage greater than the first voltage.

Abstract: Methods for controlling a ramp rate of an output voltage derived from one or more charge pumps and reducing variation in the ramp rate due to process, voltage, and temperature (PVT) variations are described. In some embodiments, the ramp rate of the output voltage from one or more charge pumps may be controlled using a ramp rate control circuit that uses a digital counter to adjust (or step up) the output voltage from the one or more charge pumps based on a ramp rate schedule. The ramp rate schedule may specify varying output voltage levels for the one or more charge pumps during a time period in which the output voltage charges up from a first voltage to a second voltage greater than the first voltage.

Abstract: A charge pump system is formed on an integrated circuit that can be connected to an external power supply. The system includes a charge pump and a clock generator circuit. The clock circuit is coupled to provide a clock output, at whose frequency the charge pump operates and generates an output voltage from an input voltage. The clock frequency is a decreasing function of the voltage level of the external power supply. This allows for reducing power consumption in the charge pump system formed on a circuit connectable to an external power supply.

Abstract: A charge pump system can provide multiple regulated output levels, including several concurrently, in an arrangement that can reduce the area and power consumption of such a high voltage generation system. The charge pump system can be dynamically reconfigurable based on output requirements. When output level is low, but required for a large AC, DC load, the system is configured in parallel to share the load. When a higher output is required, such as for a programming in a non-volatile memory, the system is configured in serial to generate the desired high output level. The exemplary embodiment uses all of the pump units in each operation and, hence, is able to be optimized for smaller pump area and less power consumption, while still delivering the same pump ability as larger, more power consuming arrangements.

Abstract: A charge pump system uses a dynamic switching approach, where the pump connections are independent of the load for each output. One large pump is designed to be shared between all of the outputs for use during the ramp up during recovery, with each output level also have one designated pump to maintain its level when under regulation. Each small pump is designed with capability that can maintain its output at its regulation level. Each of these pumps can be tailored to the corresponding output level, such as the number of stages being higher in the pump to supply the higher output level. The large pump unit is constructed to be ample to provide sufficient drive to be able to assist in the ramp up phase for all of the outputs and has as many switches needed to connect the pump with all the needed outputs.

Abstract: A regulator system for a charge pump system divides the binary decoding into two branches. One controls a set of parallel connected resistors for fine output voltage steps. The other branch controls a serial resistor to provide the large step size. For example, a 9-bit digital input signal is split into 2 least significant for the fine adjustment and the other 7 bits for the larger adjustments. In the example of a 50 mV step size, in one current path 2 bits of the binary input then control two parallel resistors for 50 mV and 100 mV step size, and in the other current path 7 bits are used for one-hot-decode control serial resistors to provide a 200 mV step size. A unity gain operational amplifier and a high voltage device are added in between the two branches to decouple the parasitic capacitance of large parallel resistors from the other elements.

Abstract: A charge pump system uses a dynamic switching approach, where the pump connections are independent of the load for each output. One large pump is designed to be shared between all of the outputs for use during the ramp up during recovery, with each output level also have one designated pump to maintain its level when under regulation. Each small pump is designed with capability that can maintain its output at its regulation level. Each of these pumps can be tailored to the corresponding output level, such as the number of stages being higher in the pump to supply the higher output level. The large pump unit is constructed to be ample to provide sufficient drive to be able to assist in the ramp up phase for all of the outputs and has as many switches needed to connect the pump with all the needed outputs.

Abstract: A regulator system for a charge pump system divides the binary decoding into two branches. One controls a set of parallel connected resistors for fine output voltage steps. The other branch controls a serial resistor to provide the large step size. For example, a 9-bit digital input signal is split into 2 least significant for the fine adjustment and the other 7 bits for the larger adjustments. In the example of a 50 mV step size, in one current path 2 bits of the binary input then control two parallel resistors for 50 mV and 100 mV step size, and in the other current path 7 bits are used for one-hot-decode control serial resistors to provide a 200 mV step size. A unity gain operational amplifier and a high voltage device are added in between the two branches to decouple the parasitic capacitance of large parallel resistors from the other elements.

Abstract: A charge pump system can provide multiple regulated output levels, including several concurrently, in an arrangement that can reduce the area and power consumption of such a high voltage generation system. The charge pump system can be dynamically reconfigurable based on output requirements. When output level is low, but required for a large AC, DC load, the system is configured in parallel to share the load. When a higher output is required, such as for a programming in a non-volatile memory, the system is configured in serial to generate the desired high output level. The exemplary embodiment uses all of the pump units in each operation and, hence, is able to be optimized for smaller pump area and less power consumption, while still delivering the same pump ability as larger, more power consuming arrangements.

Abstract: A level shifter circuit is presented that can apply a negative voltage level to non-selected blocks while still being able to drive a high positive level when selected. An exemplary embodiment presents a negative level shifter that is not susceptible to low voltage pfet breakdown. This allows for a high voltage level shifter (transfer gate) that can drive a negative level for unselected blocks and, when enabled for a selected block, can still drive a positive high voltage level. By using a pair of low voltage PMOS device whose n-wells share the same level as other PMOS transistors in the design, layout area can be minimized. The gates of this pair of PMOSs are connected to VSS, thereby preventing these low voltage PMOS devices from thin oxide breakdown.