Abstract: A microprocessor includes a first and second hardware data prefetchers configured to prefetch data into the microprocessor according to first and second respective algorithms, which are different. The second prefetcher is configured to detect a memory access pattern within a memory region and responsively prefetch data from the memory region according the second algorithm. The second prefetcher is further configured to provide to the first prefetcher a descriptor of the memory region. The first prefetcher is configured to stop prefetching data from the memory region in response to receiving the descriptor of the memory region from the second prefetcher. The second prefetcher also provides to the first prefetcher a communication to resume prefetching data from the memory region, such as when the second prefetcher subsequently detects that a predetermined number of memory accesses to the memory region are not in the memory access pattern.

Abstract: An apparatus including a synchronous lag receiver that receives one of a plurality of radially distributed strobes and a data bit, and that delays registering of the data bit by a propagation time. The synchronous lag receiver has a first plurality of matched inverters, a first mux, and a bit receiver. The first plurality of matched inverters generates successively delayed versions of the data bit. The first mux receives a value on a lag bus that indicates the propagation time, and selects one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver receives the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and registers the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of distributed strobe signals.

Abstract: An apparatus including a Joint Test Action Group (JTAG) interface and a bit lag control element. The JTAG interface receives information that indicates an amount to adjust a propagation time. The bit lag control element measures the propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and generates a value indicating an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value indicating the propagation time. The adjust logic adjusts the second value by the amount prescribed by the JTAG interface to yield a third value. The gray encoder gray encodes the third value to generate the value on the lag bus.

Abstract: A microprocessor includes a translation lookaside buffer, a request to load a page table entry into the microprocessor generated in response to a miss of a virtual address in the translation lookaside buffer, and a prefetch unit. The prefetch unit receives a physical address of a first cache line that includes the requested page table entry and responsively generates a request to prefetch into the microprocessor a second cache line that is the next physically sequential cache line to the first cache line.

Abstract: A microprocessor includes a main processor and a service processor. The service processor is configured to detect and break a deadlock/livelock condition in the main processor. The service processor detects the deadlock/livelock condition by detecting the main processor has not retired an instruction or completed a processor bus transaction for a predetermined number of clock cycles. In response to detecting the deadlock/livelock condition in the main processor, the service processor causes arbitration requests to a cache memory to be captured in a buffer, analyzes the captured requests to detect a pattern that may indicate a bug causing the condition and performs actions associated with the pattern to break the deadlock/livelock. The actions include suppression of arbitration requests to the cache, suppression of comparisons cache request addresses and killing requests to access the cache.

Abstract: A microprocessor includes functional units and control registers writeable to cause the functional units to institute actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state. Examples of the actions include in-order vs. out-of-order execution, serial vs. parallel cache access and single vs. multiple instruction issue, retire, translation and/or formatting per clock cycle. The actions may be instituted only if additional conditions exist, such as residing in the lowest performance running state for a minimum time, not running in a higher performance state for more than a maximum time, a user did not disable the feature, the microprocessor supports multiple running states and the operating system supports multiple running states.

Abstract: A signal generation device is provided to generate an output signal with constant frequency. The signal generation device includes a frequency-control circuit and a voltage-controlled delay line. The frequency-control circuit includes a pulse generator, generating a reference pulse signal according to a transition of the reference signal and a comparison pulse signal according to a transition of the comparison result signal, to re-shape the reference signal and the comparison result signal into narrow pulses suitable for clocking and resetting flip-flops.

Abstract: Disclosed are various embodiments for providing networked applications that are segmented into multiple client-cached executable modules. Multiple networked applications are provided by an application server, and a module cache is maintained in a client. The client obtains a user invocation of a particular functionality associated with a networked application. One of the modules associated with the particular functionality is obtained by the client from the application server over a network in response to determining that the module is not already in the module cache. The module is executed by the client to provide the particular functionality. A data cache may be implemented that includes data blocks that have been used, are being used, or are predicted to be used by the networked application.

Abstract: An embodiment of the invention provides a calibration method for an initial discharging curve of a battery. The method includes: acquiring an initial discharging curve of a battery; measuring a first open circuit voltage at a first time point and a second open circuit voltage at a second time point; according to the initial discharging curve, acquiring a first discharge capacity corresponding to the first open circuit voltage and a second discharge capacity corresponding to the second open circuit voltage according to the initial discharging curve; calculating an ideal discharge capacity according to the first discharge capacity and the second discharge capacity; measuring an real discharge capacity between the first time point and the second time point; determining a total discharge capacity difference according to the ideal discharge capacity and the real discharge capacity to calibrate the initial discharging curve to generate a current discharging curve.

Abstract: An embodiment of the invention provides a rechargeable battery module including a battery bank having serial connected battery units, a charging transistor providing a charging current to the battery bank, a balancing circuit for detecting and balancing voltage values of battery units and battery bank and a control chip. When a first voltage value of a first battery unit reaches a charge-off voltage, the control chip estimates a first unbalanced voltage difference between the first voltage and the minimal voltage among battery units. The control chip disables the charging transistor and estimates a second unbalanced voltage difference between voltages of the first battery unit and the battery unit having a minimal voltage. The control chip enables the balancing circuit to balance the first battery unit. When the voltage of the first battery is dropped by a calibration target, the charging transistor is enabled.

Abstract: A rechargeable battery module including a plurality of battery cells connected in series, a charging transistor, a balancing circuit and a control chip. The charging transistor is operative to convey a charging current to charge the battery cells. Based on voltage levels of the battery cells, the control chip disables the charging transistor and controls the balancing circuit to perform a first stage battery balance process. After finishing the first stage battery balance process, the control chip enables the charging transistor to charge the battery cells again. After being switched to a constant voltage charging mode, the control chip controls the balancing circuit based on the voltage levels of the battery cells to perform a second stage battery balance process.

Abstract: A hub device includes an upstream port, multiple downstream ports, a first and a second sub-hub module, a data-format detector, a transaction translator, and a controller. The upstream port is coupled to a host device supporting a first and/or a second data format. Each downstream port is coupled to one of a plurality of slave devices supporting a first and/or a second data format. The first sub-hub module supports transmission of data in the first data format. The second sub-hub module supports transmission of data in the second data format. The data-format detector detects the data format supported by the host device and the slave devices. The transaction translator transforms the data format between the first data format and the second data format. The controller determines whether to control the transaction translator to perform data-format transformation.

Abstract: Methods for error checking and correcting (ECC) in a memory module including at least one memory unit are provided. The method includes the steps of: receiving input data from the memory unit; performing, by a first ECC module, a first ECC operation to the input data and generating a decoding result which indicates whether decoding was successful; and determining whether to activate a second ECC module to perform a second ECC operation to the input data according to the decoding result, wherein the first and second ECC modules respectively utilize a first method and a second method, wherein the first method applies a ECC with a first fault tolerant quantity for error correction and the second method applies a ECC with a second fault tolerant quantity for error correction, and the second fault tolerant quantity is larger than the first fault tolerant quantity.

Abstract: A method implemented in a graphics engine for decoding image blocks to derive an original image is provided. The method comprises receiving at least one encoded image data block at a block decoder, the at least one encoded image data block comprising a plurality of codewords and a bitmap. The method further comprises determining a block type based on the plurality of codewords and selecting a decoder unit among a plurality of decoder units in accordance with the block type.

Abstract: An apparatus is provided for charging a Universal Serial Bus (USB) device according to an optimal charging mode. The apparatus includes a charging module that is configured to obtain a descriptor from the USB device upon detection of the USB device on a USB bus. The charging module includes one or more descriptor entries disposed in a memory and a controller. The one or more descriptor entries include descriptor data, for matching the descriptor to a specific descriptor entry, and charging data, that specifies the optimal charging mode for the USB device. The controller is coupled to the memory, and is configured to match the descriptor to the specific descriptor entry, and is configured to initiate the optimal charging mode on the USB bus according to the charging data.

Abstract: An apparatus is provided for coupling a Universal Serial Bus (USB) device and a USB host. The apparatus includes a memory and a controller. The memory includes one or more descriptor entries. The controller is configured to obtain a descriptor of the USB device upon detection of the USB device on a USB bus, and compare the descriptor to a specific descriptor entry to generate a comparing result. Then the controller enables or disables a link path between the USB host and the USB device according the comparing result.

Abstract: A bridging device and a power saving method thereof are disclosed. When a bridging chip of the bridging device receives a power saving command transferred from a host and thereby enters a power saving state, a voltage converter of the bridging device is disabled accordingly and a selection circuit selects to couple a bus voltage to the bridging chip to power the bridging chip. The bus voltage is transferred from the host through a power pin of a connector of the bridging device. The connector is coupled to the host.

Abstract: A bridging device and a power saving method thereof are disclosed. The disclosed bridging device includes a connector, a connection detector and a bridging chip. The connector is operative to connect to a host and includes a power pin and a command pin. The connection detector is coupled to the power pin to determine whether the connector is floating, and, outputs a linked signal when the connection is non-floating. The bridging chip is coupled to the command pin and the connection detector. When the bridging chip receives a power saving command transferred from the host via the command pin and the linked signal transferred from the connection detector, the bridging chip executes a power saving operation.

Abstract: An electrostatic discharge protection device, having a P-type semiconductor substrate set as floating; a first N-well and a second N-well formed in the P-type substrate; a first P-doped region and a second P-doped region formed in the first N-well and the second N-well, respectively. The first N-well and the first P-doped region form a first diode, and the second N-well and the second P-doped region form a second diode. A first N-doped region and a second N-doped region formed in the first N-well and the second N-well respectively. A third P-doped region is formed in the P-type substrate, wherein the third P-doped region is disposed between the first N-well and the second N-well, and the third P-doped region is electrically connected to the first N-doped region and the second P-doped region.

Abstract: A duty adjustment circuit is provided. The duty adjustment circuit is used to adjust a duty cycle of a first driving signal. The duty adjustment circuit includes a filter, a first comparator, and a first duty adjustor. The filter receives a comparison result signal and filters the comparison result signal to generate a duty information signal. The duty information signal indicates a duty cycle of the comparison result signal. The first comparator receives the duty information signal and determines whether a direct-current (DC) level of the duty information signal falls into a predefined voltage range to generate a first adjustment signal. The first duty adjustor receives the first adjustment signal and the first driving signal and adjusts the duty cycle of the first driving signal according to the first adjustment signal.