Patents by Inventor Viacheslav Anatolyevich DUBEYKO

Viacheslav Anatolyevich DUBEYKO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11705207
    Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: July 18, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
  • Publication number: 20210082520
    Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.
    Type: Application
    Filed: November 24, 2020
    Publication date: March 18, 2021
    Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
  • Patent number: 10885985
    Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 5, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
  • Patent number: 10678446
    Abstract: Novel technology for data object processing may include a system comprising a non-transitory memory; a non-transitory storage device; and a storage logic communicatively coupled to the non-transitory storage device and the non-transitory memory. The storage logic may be executable to perform operations comprising preparing a first log payload in the non-transitory memory; generating a first log bitmap describing a set of states for a set of logical blocks of an erase block of the non-transitory storage device; generating a first log including the first log bitmap and the first log payload; and storing the first log in the erase block of the non-transitory storage device.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: June 9, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Viacheslav Anatolyevich Dubeyko
  • Patent number: 10528426
    Abstract: Systems and methods are disclosed for recovering from various types of data and process corruptions at a data processing unit of a plurality of data processing units each coupled with a non-volatile memory divided into a plurality of selectable locations, in a system absent a central processing unit. In some embodiments a data processing unit is configured to determine validity of an allocation table of the data processing unit, retrieve a process descriptor from the allocation table, parse the non-volatile memory for a first set of process data corresponding to the process descriptor, determine validity of the first set of process data corresponding to the process descriptor and attempt to recover the first set of process data in accordance with a determination that the first set of process data is invalid.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: January 7, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Viacheslav Anatolyevich Dubeyko, Luis Vitorio Cargnini
  • Patent number: 10521306
    Abstract: Systems and methods are disclosed for maintaining a status of a respective data processing unit (DPU) of a plurality of data processing units, each coupled to non-volatile memory. In some embodiments a first DPU is configured to execute one or more persistent processes, wherein the one or more processes persist in the non-volatile memory over power cycles, generate a first broadcast message upon completion of a first persistent process, transmit the first broadcast message to a set of DPUs associated with monitoring the first DPU, receive a second broadcast message from a second DPU of the set of DPUs and assign a value indicating an active status for the second DPU in a status table to track the status of each DPU of the set of DPUs.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 31, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Viacheslav Anatolyevich Dubeyko, Luis Vitorio Cargnini
  • Patent number: 10467074
    Abstract: Systems and methods are disclosed for a journal for a storage class memory device. The storage class memory device may execute an access command for a first page in the storage class memory device. The storage class memory device may also determine whether a failure occurred while executing the access command. The storage class memory device may create an entry in a journal for the storage class memory device if a failure occurred while executing the access command. The storage class memory device may refrain from creating the entry if a failure does not occur while executing the access command.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: November 5, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Kiran Kumar Gunnam, Viacheslav Anatolyevich Dubeyko
  • Patent number: 10359953
    Abstract: Systems and methods for offloading data transformation from a host to a hybrid solid state drive (HSSD) are described. In one such method, the HSSD receives initial data from the host and stores the data at a first non-volatile memory (NVM). The HSSD receives a transformation command from the host to offload data transformation. The HSSD copies the data from the first NVM to a second NVM that is configured to provide a finer granularity of data access than that of the first NVM. Then the HSSD transforms the data at the second NVM utilizing the configured processing circuit. The HSSD may store the result in the first NVM and/or second NVM, and send it to the host.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: July 23, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
  • Patent number: 10346266
    Abstract: A non-volatile storage system is configured to reclaim bad blocks. One embodiment includes determining that a block of non-volatile memory cells is a bad block, leaving the block idle for a period of time to allow for self-curing of the block, verifying success of the self-curing, refreshing the block, verifying that the refresh was successful and subsequently using the block to store host data.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: July 9, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Viacheslav Anatolyevich Dubeyko, Seung-Hwan Song
  • Publication number: 20190163493
    Abstract: Systems and methods are disclosed for recovering from various types of data and process corruptions at a data processing unit of a plurality of data processing units each coupled with a non-volatile memory divided into a plurality of selectable locations, in a system absent a central processing unit. In some embodiments a first data processing unit is configured to receive instructions to execute a parent process from a second data processing unit and transmit instructions to execute a child process associated with the parent process to a third data processing unit. The first data processing unit may further be configured to determine occurrence of a process failure at the third data processing unit and re-assign the child process for execution.
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventors: VIACHESLAV ANATOLYEVICH DUBEYKO, LUIS VITORIO CARGNINI
  • Publication number: 20190163562
    Abstract: Systems and methods are disclosed for recovering from various types of data and process corruptions at a data processing unit of a plurality of data processing units each coupled with a non-volatile memory divided into a plurality of selectable locations, in a system absent a central processing unit. In some embodiments a data processing unit is configured to determine validity of an allocation table of the data processing unit, retrieve a process descriptor from the allocation table, parse the non-volatile memory for a first set of process data corresponding to the process descriptor, determine validity of the first set of process data corresponding to the process descriptor and attempt to recover the first set of process data in accordance with a determination that the first set of process data is invalid.
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventors: VIACHESLAV ANATOLYEVICH DUBEYKO, LUIS VITORIO CARGNINI
  • Publication number: 20190155703
    Abstract: A non-volatile storage system is configured to reclaim bad blocks. One embodiment includes determining that a block of non-volatile memory cells is a bad block, leaving the block idle for a period of time to allow for self-curing of the block, verifying success of the self-curing, refreshing the block, verifying that the refresh was successful and subsequently using the block to store host data.
    Type: Application
    Filed: January 22, 2019
    Publication date: May 23, 2019
    Applicant: Western Digital Technologies, Inc.
    Inventors: Viacheslav Anatolyevich Dubeyko, Seung-Hwan Song
  • Patent number: 10290353
    Abstract: NAND cell error remediation technologies are disclosed. The remediation technologies are applicable to 3D NAND. In one example, a storage device may include a processor and a memory device comprising NAND flash memory. The processor is configured to detect an error condition associated with a first page of the NAND flash memory, and determine whether the error condition is associated with a read disturbance or with a retention error. The processor is configured to initiate, if the error condition is associated with the read disturbance, a refresh operation with respect to the page to write data stored at the first page to a second page of the NAND flash memory, and initiate, if the error condition is associated with the retention error, a reprogramming operation with respect to the page to rewrite the data stored at the first page to the first page of the NAND flash memory.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: May 14, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Seung-Hwan Song, Viacheslav Anatolyevich Dubeyko, Zvonimir Z. Bandic
  • Patent number: 10223216
    Abstract: A non-volatile storage system is configured to reclaim bad blocks. One embodiment includes determining that a block of non-volatile memory cells is a bad block, leaving the block idle for a period of time to allow for self-curing of the block, verifying success of the self-curing, refreshing the block, verifying that the refresh was successful and subsequently using the block to store host data.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 5, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Viacheslav Anatolyevich Dubeyko, Seung-Hwan Song
  • Publication number: 20190034281
    Abstract: Systems and methods are disclosed for maintaining a status of a respective data processing unit (DPU) of a plurality of data processing units, each coupled to non-volatile memory. In some embodiments a first DPU is configured to execute one or more persistent processes, wherein the one or more processes persist in the non-volatile memory over power cycles, generate a first broadcast message upon completion of a first persistent process, transmit the first broadcast message to a set of DPUs associated with monitoring the first DPU, receive a second broadcast message from a second DPU of the set of DPUs and assign a value indicating an active status for the second DPU in a status table to track the status of each DPU of the set of DPUs.
    Type: Application
    Filed: July 27, 2017
    Publication date: January 31, 2019
    Inventors: VIACHESLAV ANATOLYEVICH DUBEYKO, LUIS VITORIO CARGNINI
  • Publication number: 20190018601
    Abstract: Novel technology for data object processing may include a system comprising a non-transitory memory; a non-transitory storage device; and a storage logic communicatively coupled to the non-transitory storage device and the non-transitory memory. The storage logic may be executable to perform operations comprising preparing a first log payload in the non-transitory memory; generating a first log bitmap describing a set of states for a set of logical blocks of an erase block of the non-transitory storage device; generating a first log including the first log bitmap and the first log payload; and storing the first log in the erase block of the non-transitory storage device.
    Type: Application
    Filed: July 11, 2017
    Publication date: January 17, 2019
    Inventor: Viacheslav Anatolyevich Dubeyko
  • Patent number: 10114795
    Abstract: In one example, a device includes a non-volatile memory divided into a plurality of selectable locations, wherein the selectable locations are grouped into a plurality of data lines; one or more processing units (PUs) coupled to the non-volatile memory, each of the PUs associated with a data line of the plurality of data lines, the one or more processing units comprising one or more reconfigurable PUs, the one or more PUs configured to: manipulate, based on one or more instruction sets, data in an associated data line to generate results that are stored in selectable locations of the associated data line reserved to store results of the manipulation; determine which of the instruction sets are most frequently used by the one or more PUs to manipulate data; and reconfigure the one or more reconfigurable PUs to manipulate data using the determined most frequently used instruction sets.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 30, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
  • Publication number: 20180188973
    Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
  • Publication number: 20180189155
    Abstract: Systems and methods are disclosed for a journal for a storage class memory device. The storage class memory device may execute an access command for a first page in the storage class memory device. The storage class memory device may also determine whether a failure occurred while executing the access command. The storage class memory device may create an entry in a journal for the storage class memory device if a failure occurred while executing the access command. The storage class memory device may refrain from creating the entry if a failure does not occur while executing the access command.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Kiran Kumar GUNNAM, Viacheslav Anatolyevich DUBEYKO
  • Publication number: 20180189230
    Abstract: In one example, a device includes a non-volatile memory divided into a plurality of selectable locations, wherein the selectable locations are grouped into a plurality of data lines; one or more processing units (PUs) coupled to the non-volatile memory, each of the PUs associated with a data line of the plurality of data lines, the one or more processing units comprising one or more reconfigurable PUs, the one or more PUs configured to: manipulate, based on one or more instruction sets, data in an associated data line to generate results that are stored in selectable locations of the associated data line reserved to store results of the manipulation; determine which of the instruction sets are most frequently used by the one or more PUs to manipulate data; and reconfigure the one or more reconfigurable PUs to manipulate data using the determined most frequently used instruction sets.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko