Patents by Inventor Viacheslav Anatolyevich DUBEYKO

Viacheslav Anatolyevich DUBEYKO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10013346
    Abstract: A journaling approach is used to distribute data of different sizes between areas of a segment's log on a physical NAND flash erase block. The Main area contains large, contiguous extents of data, and the Journal area contains logical blocks of small data. An Updates area also contains updates that are pending. One disclosed embodiment includes storing a first file fragment associated with a file in a journal area of a log, where a size of the file fragment is less than a physical NAND flash page size limit, receiving a second file fragment associated with the file, combining the first file fragment and the second file fragment when a combined size of the fragments is equal to the physical NAND flash page size limit, storing the combined fragments in a main area of a second log, receiving an update associated with the combined fragments, and storing the update in an updates area of a third log.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: July 3, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Viacheslav Anatolyevich Dubeyko, Cyril Guyot
  • Publication number: 20180173441
    Abstract: Systems and methods for offloading data transformation from a host to a hybrid solid state drive (HSSD) are described. In one such method, the HSSD receives initial data from the host and stores the data at a first non-volatile memory (NVM). The HSSD receives a transformation command from the host to offload data transformation. The HSSD copies the data from the first NVM to a second NVM that is configured to provide a finer granularity of data access than that of the first NVM. Then the HSSD transforms the data at the second NVM utilizing the configured processing circuit. The HSSD may store the result in the first NVM and/or second NVM, and send it to the host.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 21, 2018
    Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
  • Publication number: 20180173419
    Abstract: A storage device includes a controller, a first memory device with a first type of non-volatile memory, and a second memory device with a second type of non-volatile memory. The second type of non-volatile memory may be byte-addressable and may exhibit a lower latency for write operations than the first type of non-volatile memory. The controller may be configured to receive, from a host device, a write request that include a data log. The data log may include first data associated with a first logical block address and second data associated with a second logical block address. The controller may also be configured to, responsive to determining that a size of the data is at least a threshold size, store at least a portion of the first data to the first memory device. The controller may also be configured to, responsive to determining that the size of the first data does not satisfy the threshold size, store the data to the second memory device.
    Type: Application
    Filed: December 21, 2016
    Publication date: June 21, 2018
    Inventor: Viacheslav Anatolyevich Dubeyko
  • Publication number: 20180068726
    Abstract: NAND cell error remediation technologies are disclosed. The remediation technologies are applicable to 3D NAND. In one example, a storage device may include a processor and a memory device comprising NAND flash memory. The processor is configured to detect an error condition associated with a first page of the NAND flash memory, and determine whether the error condition is associated with a read disturbance or with a retention error. The processor is configured to initiate, if the error condition is associated with the read disturbance, a refresh operation with respect to the page to write data stored at the first page to a second page of the NAND flash memory, and initiate, if the error condition is associated with the retention error, a reprogramming operation with respect to the page to rewrite the data stored at the first page to the first page of the NAND flash memory.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 8, 2018
    Inventors: Seung-Hwan Song, Viacheslav Anatolyevich Dubeyko, Zvonimir Z. Bandic
  • Publication number: 20170139822
    Abstract: A journaling approach is used to distribute data of different sizes between areas of a segment's log on a physical NAND flash erase block. The Main area contains large, contiguous extents of data, and the Journal area contains logical blocks of small data. An Updates area also contains updates that are pending. One disclosed embodiment includes storing a first file fragment associated with a file in a journal area of a log, where a size of the file fragment is less than a physical NAND flash page size limit, receiving a second file fragment associated with the file, combining the first file fragment and the second file fragment when a combined size of the fragments is equal to the physical NAND flash page size limit, storing the combined fragments in a main area of a second log, receiving an update associated with the combined fragments, and storing the update in an updates area of a third log.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 18, 2017
    Inventors: Viacheslav Anatolyevich DUBEYKO, Cyril GUYOT