Abstract: A method and apparatus for detecting an etching endpoint of a film on a substrate whereby a first excitation beam of light having a prescribed wavelength is provided, the first light beam substantially containing only a first harmonic component of light at that wavelength. The first light beam is directed at a prescribed incident angle to an interface between the film and the substrate, the first light beam being reflected off the interface to thereby provide a second light beam, the second light beam containing the first harmonic component of the first light beam and a generated second harmonic component. The generated second harmonic component is detected and a first output signal representative thereof is provided. A generated second harmonic component reference of the first light beam is produced and a second output signal representative of a generated second harmonic component reference is provided.

Abstract: A non-intrusive, in-situ monitoring technique and apparatus is used for evaluating the presence and extent of a critical contaminating or passivating layer on a transparent sample, prior to a subsequent process step. A multiple internal reflection apparatus and method without the need for aligning mirrors reduces the time to maximize the light intensity through the sample and to the detector and eliminates the intensity loss due to reflection from each mirror. The technique and apparatus can be used to monitor for a critical hydrogen passivation layer so that it is maintained on the silicon surface right up to the point at which the reactants are introduced for the deposition. The in-situ monitoring and process control technique uses Fourier Transform Infrared Spectroscopy with Multiple Internal Reflections (FTIRS-MIR) which looks at the Si--H bond vibration. Apparatus implementing the technique provides a means of insuring reproducibility in films through direct monitoring of the passivating layer.

Abstract: A method and apparatus for measuring with monolayer sensitivity in real-time the condition of a sample, includes a device for producing a modulated and collimated, p-polarized excitation light beam, a device for directing the p-polarized beam to a surface of the sample such that an angle of incidence of the p-polarized light beam with respect to the normal of the surface is at the Brewster angle, first and second reflecting devices between which the sample is positioned, a mechanism for adjusting a distance between the first and second reflecting devices to adjust a number of interactions of the p-polarized excitation light beam with the sample surfaces, and a detector for detecting the p-polarized light beam output intensity distribution with respect to frequency front the sample surfaces. The reflecting devices and the sample are adjustably maintained parallel to one another to thereby maintain the Brewster angle of the input excitation light beam with respect to the normal of the sample surface.

Abstract: A method of fabricating a semiconductor structure, comprising the steps of: providing a monocrystalline semiconductor device region of a first conductivity type; forming a layer of intrinsic monocrystalline semiconductor material over the device region; forming a layer of insulating material over the layer of intrinsic monocrystalline semiconductor material; forming a conductive contact over a portion of the layer of insulating material; forming an aperture extending through the conductive contact, and the layers of insulating material and intrinsic monocrystalline semiconductor material to define an aperture exposing a selected portion of the layer of intrinsic monocrystalline semiconductor material; and forming a layer of semiconductor material of a second conductivity type including a monocrystalline portion disposed epitaxially over the device region portion and a polycrystalline portion extending onto the wall of the conductive contact within the aperture.

Abstract: A method of forming a thin silicon SOI layer by wafer bonding, the thin silicon SOI layer being substantially free of defects upon which semiconductor structures can be subsequently formed, is disclosed.

Abstract: A method for isolating a film from a substrate 50 includes the steps of: providing an N+ layer 52 on the substrate 50; forming an insulation layer 54 onto the N+ doped layer 52; etching a pair of trenches 56, 58 through the insulation layer 52 to thereby form an isolation region 60 of insulation material; laterally etching a cavity 62 underneath the isolation region; and, forming a film 64 onto the isolation region.

Abstract: A method for isolating areas of silicon from a substrate 50 includes the steps of: providing a buried N+ region 52 in the substrate; forming an intrinsic epitaxial layer 12 onto the N+ region; etching trenches 18, 20 through the intrinsic epitaxial layer to thereby form a desired isolation region 16 of intrinsic epitaxial material; laterally etching a cavity 22 underneath the desired isolation region; and, forming an insulation layer 24 of insulation material along the bottom of the desired isolation region exposed by the former etching steps.

Abstract: An interferometer 10 for measuring the position of the process surface 21 of a substrate 20 includes a coherent light source 12 for providing a light beam 14 which is partially transmitted and partially reflected by a beam splitter 16. The reflected light beam 18 is reflected off of the process surface 21 and the transmitted light beam 30 is reflected off of a translator 32 which vibrates a predetermined distance at a predetermined frequency. The phase shift between the light beams 22, 31 reflected off of translator 32 and the process surface 21 is measured using a photodetector 24, which provides an output signal 26 to a feedback servo unit 28. The servo unit 28 provides an output signal 38 which controls the vibration of translator 32. The output signal 38 of servo unit 28 is also indicative of the position of the process surface 21.

Abstract: A semiconductor structure including a doped semiconductor substrate defining a surface. A buffer layer of epitaxial semiconductor material overlies the substrate surface, the buffer layer having a relatively higher dopant concentration than the substrate and being virtually free from oxygen precipitation. A layer of intrinsic semiconductor material overlies the buffer layer, and a device layer of epitaxial semiconductor material is situated on the intrinsic layer. The device layer is formed to have a relatively lower dopant concentration than the first layer. Isolation regions extend from a surface of the device layer into the buffer layer for forming an electrically isolated device region in the device layer. At least one active device is formed in the isolated device region.

Abstract: A semiconductor structure including a doped semiconductor substrate defining a surface. A buffer layer of epitaxial semiconductor material overlies the substrate surface, the buffer layer having a relatively higher dopant concentration than the substrate and being virtually free from oxygen precipitation. A layer of intrinsic semiconductor material overlies the buffer layer, and a device layer of epitaxial semiconductor material is situated on the intrinsic layer. The device layer is formed to have a relatively lower dopant concentration than the first layer. Isolation regions extend from a surface of the device layer into the buffer layer for forming an electrically isolated device region in the device layer. At least one active device is formed in the isolated device region.

Abstract: A novel method of employing selective epitaxial growth, in which interdevice isolation is intrinsically formed. Problems stemming from formation of all active device elements within selective epitaxial growth regions are addressed. Additionally, there is shown a novel transistor array formed according to the method of the invention.

Abstract: A method of simultaneously producing doped silicon filled trenches in areas where a substrate contact is to be produced and trench isolation in other areas. Borosilicate glass lines the sidewalls of those trenches where a contact is desired and undoped epitaxially grown silicon fills all the trenches. Subsequent heat processing causes the boron in the borosilicate to dope the epitaxial silicon in those trenches. In the other trenches, the silicon fill remains undoped except at the bottom where a channel stop exists, thereby forming isolation trenches. The contacts formed over the trenches may be formed by selectively deposition of a highly doped silicon into an opening that overlies a portion of the trench and the adjacent substrate surface.

Abstract: A novel method of employing selective epitaxial growth, in which interdevice isolation is intrinsically formed. Problems stemming from formation of all active device elements within selective epitaxial growth regions are addressed. Additionally, there is shown a novel transistor array formed according to the method of the invention.

Abstract: A method for forming epitaxial grown silicon structure having substantially defect free outer surfaces and resulting structure is provided. A silicon substrate is provided, on which an epitaxial silicon crystal is grown. The outer surface layer of the silicon epitaxially grown silicon crystal will contain defective material which is removed by oxidation of the outer layer to silicon dioxide. This removes the defect containing outer layer, creating a new outer layer which is substantially defect free.

Abstract: A method of simultaneously producing doped silicon filled trenches in areas where a substrate contact is to be produced and trench isolation in other areas. Borosilicate glass lines the sidewalls of those trenches where a contact is desired and undoped epitaxially grown silicon fills all the trenches. Subsequent heat processing causes the boron in the borosilicate to dope the epitaxial silicon in those trenches. In the other trenches, the silicon fill remains undoped except at the bottom where a channel stop exists, thereby forming isolation trenches. The contacts formed over the trenches may be formed by selectively deposition of a highly doped silicon into an opening that overlies a portion of the trench and the adjacent substrate surface.

Abstract: A novel method of employing selective epitaxial growth, in which interdevice isolation is intrinsically formed. Problems stemming from formation of all active device elements within selective epitaxial growth regions are addressed. Additionally, there is shown a novel transistor array formed according to the method of the invention.

Abstract: The void-free pattern of isolation in a semiconductor substrate is described. There is contained within a semiconductor body a pattern of substantially vertically sided trenches. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. The depth of the pattern of trenches is greater than about 3 micrometers. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to between about 500 to 1500 nanometers from the upper surface of the trenches. A capping second insulating layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer for isolation of the pattern of trenches from the ambient.

Abstract: A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer.

Abstract: A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer.

Abstract: Isolation regions in a semiconductor substrate are formed by covering at least one of the surfaces within a trench within the substrate with non-nucleating material, providing a layer of nucleating material on at least one surface of the non-nucleating material and then filling the trench with polycrystalline silicon or epitaxial silicon or both.