Patents by Inventor Victor Moroz

Victor Moroz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8219961
    Abstract: An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: July 10, 2012
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Dipankar Pramanik, Kishore Singhal, Xi-Wei Lin
  • Publication number: 20120011479
    Abstract: Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.
    Type: Application
    Filed: September 20, 2011
    Publication date: January 12, 2012
    Applicant: SYNOPSYS, INC.
    Inventors: Victor Moroz, Munkang Choi, Xi-Wei Lin
  • Patent number: 8086990
    Abstract: Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that are available as inputs to a second, stress-insensitive, transistor model. The second transistor model may for example be the same as the first model, with its stress sensitivity disabled. Thereafter, a substitute stress analyzer can be used to determine a stress-adjusted value for the first performance measure, and the mathematical relationship can be used to convert that value into specific values for the one or more instance parameters. These values are then provided to the second transistor model for use in simulating the characteristics of the particular transistor during circuit simulation.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: December 27, 2011
    Assignee: Synopsys, Inc.
    Inventors: Xi-Wei Lin, Victor Moroz, Dipankar Pramanik
  • Publication number: 20110309453
    Abstract: Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
    Type: Application
    Filed: August 30, 2011
    Publication date: December 22, 2011
    Inventors: Victor Moroz, Dipankar Pramanik, Xi-Wei Lin
  • Patent number: 8069430
    Abstract: Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: November 29, 2011
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Xi-Wei Lin, Dipankar Pramanik
  • Patent number: 8035168
    Abstract: Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: October 11, 2011
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Dipankar Pramanik, Xi-Wei Lin
  • Publication number: 20110219351
    Abstract: An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.
    Type: Application
    Filed: May 20, 2011
    Publication date: September 8, 2011
    Applicant: SYNOPSYS, INC.
    Inventors: Victor Moroz, Dipankar Pramanik, Kishore Singhal, Xi-Wei Lin
  • Publication number: 20110212601
    Abstract: Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.
    Type: Application
    Filed: May 9, 2011
    Publication date: September 1, 2011
    Applicant: Synopsys, Inc.
    Inventors: Victor Moroz, Tsu-Jae King Liu
  • Patent number: 7996795
    Abstract: A method, a computer medium storing computer instructions performing a method, and a computer with processor and memory perform stress modeling as follows. The stress model transforms a representation of a material conversion of a first material in the integrated circuit to a second material in the integrated circuit. Prior to the material conversion the first material occupies a first space having a first boundary. After the material conversion the first material and the second material together occupy a second space having a second boundary. The first space and the second space are different. The stress model performed by the computer system transforms the representation of the material conversion of the first material to the second material into: i) the first material occupying the first space having the first boundary, and ii) a strain displacement condition of the first material. The strain displacement condition is determined by a spatial change from the first boundary to the second boundary.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: August 9, 2011
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Xiaopeng Xu
  • Publication number: 20110169140
    Abstract: Roughly described, an integrated circuit device includes a substrate including a via passing therethrough, a strained electrically conductive first material in the via, the first material tending to introduce first stresses into the substrate, and a strained second material in the via, the second material tending to introduce second stresses into the substrate which at least partially cancel the first stresses. In an embodiment, SiGe is grown epitaxially on the inside sidewall of the via in the silicon wafer. SiO2 is then formed on the inside surface of the SiGe, and metal is formed down the center. The stresses introduce by the SiGe tend to counteract the stresses introduced by the metal, thereby reducing or eliminating undesirable stress in the silicon and permitting the placement of transistors in close proximity to the TSV.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 14, 2011
    Applicant: SYNOPSYS, INC.
    Inventor: VICTOR MOROZ
  • Patent number: 7968413
    Abstract: Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: June 28, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Faran Nouri, Lori D. Washington, Victor Moroz
  • Patent number: 7960232
    Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: June 14, 2011
    Assignee: Synopsys, Inc.
    Inventors: Tsu-Jae King, Victor Moroz
  • Patent number: 7949985
    Abstract: An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: May 24, 2011
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Dipankar Pramanik, Kishore Singhal, Xi-Wei Lin
  • Patent number: 7939862
    Abstract: Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: May 10, 2011
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Tsu-Jae King Liu
  • Patent number: 7926018
    Abstract: A system that generates a layout for a transistor is presented. During operation, the system receives a transistor library which includes operating characteristics of fabricated transistors correlated to transistor gate shapes. The system also receives one or more desired operating characteristics for the transistor. Next, the system determines a transistor gate shape for the transistor based on the transistor library so that a fabricated transistor with the transistor gate shape substantially achieves the one or more desired operating characteristics. The system then generates the layout for the transistor which includes the transistor gate shape.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: April 12, 2011
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Xi-Wei Lin, Mark Rubin
  • Patent number: 7897479
    Abstract: Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: March 1, 2011
    Assignee: Synopsys, Inc.
    Inventors: Xi-Wei Lin, Dipankar Pramanik, Victor Moroz
  • Patent number: 7863146
    Abstract: Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: January 4, 2011
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Dipankar Pramanik, Xi Wei Lin
  • Patent number: 7833869
    Abstract: Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon carbide material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon carbide material to form a source/drain region having a second conductivity.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: November 16, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Faran Nouri, Lori D. Washington, Victor Moroz
  • Publication number: 20100274376
    Abstract: A method, a computer medium storing computer instructions performing a method, and a computer with processor and memory perform stress modeling as follows. The stress model transforms a representation of a material conversion of a first material in the integrated circuit to a second material in the integrated circuit. Prior to the material conversion the first material occupies a first space having a first boundary. After the material conversion the first material and the second material together occupy a second space having a second boundary. The first space and the second space are different. The stress model performed by the computer system transforms the representation of the material conversion of the first material to the second material into: i) the first material occupying the first space having the first boundary, and ii) a strain displacement condition of the first material. The strain displacement condition is determined by a spatial change from the first boundary to the second boundary.
    Type: Application
    Filed: April 24, 2009
    Publication date: October 28, 2010
    Applicant: Synopsys, Inc.
    Inventors: Victor Moroz, Xiaopeng Xu
  • Publication number: 20100270597
    Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.
    Type: Application
    Filed: April 24, 2009
    Publication date: October 28, 2010
    Applicant: SYNOPSYS, INC.
    Inventors: JAMES DAVID SPROCH, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar