Abstract: Embodiments of the present invention provide an inequality indication system (IIS). The IIS provides built in test support which enables evaluation, in an on-chip digital logic circuit, of digital values as inequalities, with either a single pass/fail bit expressed on a device I/O or a readable register containing inequality evaluation results. The IIS enables the movement of value evaluation onto the device (chip) using a common simple method, well suited to address/data type structures or scan based structures, instead of off-chip, which then requires tester dependent custom code. The IIS, when enabled, overrides the TDO signal to allow it to function as an inequality indicator instead of a standard test data out signal.

Abstract: Embodiments of the present invention provide an inequality indication system (IIS). The IIS provides built in test support which enables evaluation, in an on-chip digital logic circuit, of digital values as inequalities, with either a single pass/fail bit expressed on a device I/O or a readable register containing inequality evaluation results. The IIS enables the movement of value evaluation onto the device (chip) using a common simple method, well suited to address/data type structures or scan based structures, instead of off-chip, which then requires tester dependent custom code. The IIS, when enabled, overrides the TDO signal to allow it to function as an inequality indicator instead of a standard test data out signal.

Abstract: A data communication system includes circuitry to assure components respond to variations in the time length of the valid data window or “eye” of the high speed data communication signal. A self-test portion of the system periodically injects the effects of phase jitter into the data communication signal to assure the system performs properly.

Abstract: The present invention provides a robust global timing resynchronization architecture, a multi-link communications system including the same, and a method for minimizing the effects of resynchronization signal skew, reference clock skew, and PLL static phase error variations on resynchronization of multi-link communications systems.

Abstract: A data communication system includes circuitry to assure components respond to variations in the time length of the valid data window or “eye” of the high speed data communication signal. A self-test portion of the system periodically injects the effects of phase jitter into the data communication signal to assure the system performs properly.

Abstract: A data communication system includes circuitry to assure components respond to variations in the time length of the valid data window or “eye” of the high speed data communication signal. A self-test portion of the system periodically injects the effects of phase jitter into the data communication signal to assure the system performs properly.

Abstract: The present invention provides a robust global timing resynchronization architecture, a multi-link communications system including the same, and a method for minimizing the effects of resynchronization signal skew, reference clock skew, and PLL static phase error variations on resynchronization of multi-link communications systems.

Abstract: A data communication system includes circuitry to assure components respond to variations in the time length of the valid data window or “eye” of the high speed data communication signal. A self-test portion of the system periodically injects the effects of phase jitter into the data communication signal to assure the system performs properly.

Abstract: A calibration system for a Phase Locked Loop (PLL) includes a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency. A charge pump is connected to receive an error signal from the phase/frequency detector and provide a voltage to a low pass filter. The low pass filter provides a filtered error signal to the VCO and to a comparator system. The comparator system provides a comparator output signal indicating when the polarity of the error signal exceeds a positive limit or a negative limit. A calibration means continuously provides incremental calibration inputs to the VCO, after a time delay. Thus the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift, and avoid jitter caused by an excessive rate of response to calibration inputs.

Abstract: A calibration system for a Phase Locked Loop (PLL) includes a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency. A charge pump is connected to receive an error signal from the phase/frequency detector and provide a voltage to a low pass filter. The low pass filter provides a filtered error signal to the VCO and to a comparator system. The comparator system provides a comparator output indicating when the polarity of the error signal exceeds a positive limit or a negative limit. A calibration means continuously provides incremental calibration inputs to the VCO after a time delay. Thus the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift and avoid jitter caused by an excessive rate of response to calibration inputs.