Patents by Inventor Victor Y. Lu
Victor Y. Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220379356Abstract: A cleaning device for removing contamination on a substrate holder used with an electroplating cell includes an arm, a cleaning agent supplier, a nozzle and a receiver. The cleaning agent supplier is coupled to the arm and configured to supply a cleaning agent. The nozzle is coupled to the cleaning agent supplier and configured to spray the cleaning agent onto the substrate holder to remove the contamination. The receiver is coupled to the arm and configured to receive the cleaning agent after the cleaning agent is sprayed onto the substrate holder.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Yu-Young WANG, Chung-En KAO, Victor Y. LU
-
Patent number: 11508670Abstract: A method of manufacturing a semiconductor structure includes the following operations. A wafer includes a crystal orientation represented by a family of Miller indices comprising <lmn>, wherein l2+m2+n2=1. A first chip and a second chip are over the wafer. A first edge of the first chip and a second edge of the second chip are adjacent to each other. A boundary extending in a direction between the first edge and the second edge is formed. A first included angle between the first direction and the crystal orientation is greater than or equal to 0 degree and less than 45 degrees.Type: GrantFiled: June 9, 2020Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Pu-Fang Chen, Shi-Chieh Lin, Victor Y. Lu
-
Patent number: 11433440Abstract: A cleaning device for removing contamination on a substrate holder used with an electroplating cell includes an arm, a cleaning agent supplier, a nozzle and a receiver. The cleaning agent supplier is coupled to the arm and configured to supply a cleaning agent. The nozzle is coupled to the cleaning agent supplier and configured to spray the cleaning agent onto the substrate holder to remove the contamination. The receiver is coupled to the arm and configured to receive the cleaning agent after the cleaning agent is sprayed onto the substrate holder.Type: GrantFiled: June 3, 2019Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Young Wang, Chung-En Kao, Victor Y. Lu
-
Publication number: 20220139769Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.Type: ApplicationFiled: January 19, 2022Publication date: May 5, 2022Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
-
Publication number: 20220122849Abstract: A representative method of manufacturing a silicon-on-insulator (SOI) substrate includes steps of depositing an etch stop layer on a dummy wafer, growing an epitaxial silicon layer on the etch stop layer, forming a gettering layer on the epitaxial silicon layer, bonding a buried oxide layer of a main wafer to the gettering layer, and removing the dummy wafer and etch stop layer to expose the epitaxial silicon layer. The SOI substrate has an epitaxial silicon layer adjoining the gettering layer, with the gettering layer interposed between the buried oxide layer and the epitaxial silicon layer.Type: ApplicationFiled: December 27, 2021Publication date: April 21, 2022Inventors: Pu-Fang Chen, Shi-Chieh Lin, Victor Y. Lu, Yeur-Luen Tu
-
Patent number: 11232974Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.Type: GrantFiled: August 21, 2019Date of Patent: January 25, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
-
Patent number: 11230791Abstract: Among other things, one or more systems and techniques for promoting metal plating profile uniformity are provided. A magnetic structure is positioned relative to a semiconductor wafer that is to be electroplated with metal during a metal plating process. In an embodiment, the magnetic structure applies a force that decreases an edge plating current by moving metal ions away from a wafer edge of the semiconductor wafer. In an embodiment, the magnetic structure applies a force that increases a center plating current by moving metal ions towards a center portion of the semiconductor wafer. In this way, the edge plating current has a current value that is similar to a current value of the center plating current. The similarity between the center plating current and the edge plating current promotes metal plating uniformity.Type: GrantFiled: December 31, 2019Date of Patent: January 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Ming-Chin Tsai, Chung-En Kao, Victor Y. Lu
-
Patent number: 11211259Abstract: A representative method of manufacturing a silicon-on-insulator (SOI) substrate includes steps of depositing an etch stop layer on a dummy wafer, growing an epitaxial silicon layer on the etch stop layer, forming a gettering layer on the epitaxial silicon layer, bonding a buried oxide layer of a main wafer to the gettering layer, and removing the dummy wafer and etch stop layer to expose the epitaxial silicon layer. The SOI substrate has an epitaxial silicon layer adjoining the gettering layer, with the gettering layer interposed between the buried oxide layer and the epitaxial silicon layer.Type: GrantFiled: April 20, 2018Date of Patent: December 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pu-Fang Chen, Shi-Chieh Lin, Victor Y. Lu, Yeur-Luen Tu
-
Patent number: 11111910Abstract: Cryogenic pump apparatuses include nanostructure material to achieve an ultra-high vacuum level. The nanostructure material can be mixed with either an adsorbent material or a fixed glue layer which is utilized to fix the adsorbent material. The nanostructure material's good thermal conductivity and adsorption properties help to lower working temperature and extend regeneration cycle of the cryogenic pumps.Type: GrantFiled: December 3, 2018Date of Patent: September 7, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Surendra Babu Anantharaman, Wen-Cheng Yang, Chung-En Kao, Victor Y. Lu, Wei Chin
-
Patent number: 10811263Abstract: A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber and introducing a plasma-forming gas into the PVD chamber. The plasma-forming gas is an oxygen-containing gas. The method also includes applying a radio frequency (RF) power by a power source to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. The metal target is directly electrically coupled to the power source. The method further includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.Type: GrantFiled: December 30, 2019Date of Patent: October 20, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ya-Ling Lee, Shing-Chyang Pan, Keng-Chu Lin, Wen-Cheng Yang, Chih-Tsung Lee, Victor Y. Lu
-
Publication number: 20200303324Abstract: A method of manufacturing a semiconductor structure includes the following operations. A wafer includes a crystal orientation represented by a family of Miller indices comprising <lmn>, wherein l2+m2+n2=1. A first chip and a second chip are over the wafer. A first edge of the first chip and a second edge of the second chip are adjacent to each other. A boundary extending in a direction between the first edge and the second edge is formed. A first included angle between the first direction and the crystal orientation is greater than or equal to 0 degree and less than 45 degrees.Type: ApplicationFiled: June 9, 2020Publication date: September 24, 2020Inventors: PU-FANG CHEN, SHI-CHIEH LIN, VICTOR Y. LU
-
Patent number: 10755953Abstract: The present disclosure relates to some embodiments of a method for improving processing efficiency of a cluster tool. The method comprises transferring a first lot of wafers from a transfer load lock to a designated storage load lock and transferring a second lot of wafers from the transfer load lock to the designated storage load lock while the first lot of wafers is in the transfer load lock or the designated storage load lock. The designated storage load lock has the same structure as the transfer load lock and respectively has an inner load lock portal at an interface with the first transfer chamber and an outer load lock portal on a sidewall of a front end interface. The inner load lock portal of the designated storage load lock is retained opened during processing. The outer load lock portal of the designated storage load lock is retained closed during processing.Type: GrantFiled: October 18, 2019Date of Patent: August 25, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Su-Horng Lin, Tsung-Hsun Yu, Victor Y. Lu
-
Patent number: 10714433Abstract: A method of manufacturing a semiconductor structure includes the following operations. A wafer with an orientation mark at a first crystal orientation represented by a family of Miller indices comprising <ijk> is provided, wherein i2+ j2+ k2=2. A first chip and a second chip are connected to a first surface of the wafer. A first edge of the first chip and a second edge of the second chip are adjacent to each other. A boundary extending in a direction between the first edge and the second edge is formed. The direction is not parallel to the first crystal orientation.Type: GrantFiled: May 16, 2018Date of Patent: July 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Pu-Fang Chen, Shi-Chieh Lin, Victor Y. Lu
-
Publication number: 20200176306Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.Type: ApplicationFiled: August 21, 2019Publication date: June 4, 2020Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
-
Publication number: 20200144063Abstract: A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber and introducing a plasma-forming gas into the PVD chamber. The plasma-forming gas is an oxygen-containing gas. The method also includes applying a radio frequency (RF) power by a power source to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. The metal target is directly electrically coupled to the power source. The method further includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.Type: ApplicationFiled: December 30, 2019Publication date: May 7, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ya-Ling LEE, Shing-Chyang PAN, Keng-Chu LIN, Wen-Cheng YANG, Chih-Tsung LEE, Victor Y. LU
-
Publication number: 20200131662Abstract: Among other things, one or more systems and techniques for promoting metal plating profile uniformity are provided. A magnetic structure is positioned relative to a semiconductor wafer that is to be electroplated with metal during a metal plating process. In an embodiment, the magnetic structure applies a force that decreases an edge plating current by moving metal ions away from a wafer edge of the semiconductor wafer. In an embodiment, the magnetic structure applies a force that increases a center plating current by moving metal ions towards a center portion of the semiconductor wafer. In this way, the edge plating current has a current value that is similar to a current value of the center plating current. The similarity between the center plating current and the edge plating current promotes metal plating uniformity.Type: ApplicationFiled: December 31, 2019Publication date: April 30, 2020Inventors: Ming-Chin TSAI, Chung-En KAO, Victor Y. LU
-
Publication number: 20200051837Abstract: The present disclosure relates to some embodiments of a method for improving processing efficiency of a cluster tool. The method comprises transferring a first lot of wafers from a transfer load lock to a designated storage load lock and transferring a second lot of wafers from the transfer load lock to the designated storage load lock while the first lot of wafers is in the transfer load lock or the designated storage load lock. The designated storage load lock has the same structure as the transfer load lock and respectively has an inner load lock portal at an interface with the first transfer chamber and an outer load lock portal on a sidewall of a front end interface. The inner load lock portal of the designated storage load lock is retained opened during processing. The outer load lock portal of the designated storage load lock is retained closed during processing.Type: ApplicationFiled: October 18, 2019Publication date: February 13, 2020Inventors: Su-Horng Lin, Tsung-Hsun Yu, Victor Y. Lu
-
Patent number: 10526719Abstract: Among other things, one or more systems and techniques for promoting metal plating profile uniformity are provided. A magnetic structure is positioned relative to a semiconductor wafer that is to be electroplated with metal during a metal plating process. In an embodiment, the magnetic structure applies a force that decreases an edge plating current by moving metal ions away from a wafer edge of the semiconductor wafer. In an embodiment, the magnetic structure applies a force that increases a center plating current by moving metal ions towards a center portion of the semiconductor wafer. In this way, the edge plating current has a current value that is similar to a current value of the center plating current. The similarity between the center plating current and the edge plating current promotes metal plating uniformity.Type: GrantFiled: August 21, 2013Date of Patent: January 7, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ming-Chin Tsai, Chung-En Kao, Victor Y. Lu
-
Patent number: 10522360Abstract: A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber. The method also includes introducing a plasma-forming gas into the PVD chamber, and the plasma-forming gas contains an oxygen-containing gas. The method further includes applying a radio frequency (RF) power to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. In addition, the method includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.Type: GrantFiled: October 12, 2017Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ya-Ling Lee, Shing-Chyang Pan, Keng-Chu Lin, Wen-Cheng Yang, Chih-Tsung Lee, Victor Y. Lu
-
Patent number: 10510566Abstract: Some embodiments relate to a cluster tool for semiconductor manufacturing. The cluster tool comprises a first transfer chamber having a first transfer robot. The cluster tool further comprises a designated storage chamber and a transfer load lock attached to the first transfer chamber. The cluster tool further comprises a second transfer chamber connected to the first transfer chamber through a pair of via connector chambers, the second transfer chamber having a second transfer robot. The cluster tool further comprises at least three epitaxial deposition chamber attached to the second transfer chamber. The cluster tool further comprises a control unit configured to control the second transfer robot to transfer wafers between the designated storage chamber and the transfer load lock.Type: GrantFiled: July 14, 2015Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Su-Horng Lin, Tsung-Hsun Yu, Victor Y. Lu