Abstract: A method for intelligent inline metrology is a provided. A parameter of a workpiece is measured at a first set of inspection sites on the workpiece. A determination is made as to whether a first specification is met using the measurements at the first set of inspection sites. In response to the first specification being met, the parameter is estimated at a second set of inspection sites on the workpiece. In response to the first specification being unmet, the parameter is measured at the second set of inspection sites and a determination is made as to whether a second specification is met using the measurements at the second set of inspection sites. A system for intelligent inline metrology is also provided.

Abstract: A cleaning device for removing contamination on a substrate holder used with an electroplating cell includes an arm, a cleaning agent supplier, a nozzle and a receiver. The cleaning agent supplier is coupled to the arm and configured to supply a cleaning agent. The nozzle is coupled to the cleaning agent supplier and configured to spray the cleaning agent onto the substrate holder to remove the contamination. The receiver is coupled to the arm and configured to receive the cleaning agent after the cleaning agent is sprayed onto the substrate holder.

Abstract: Some embodiments relate to a cluster tool for semiconductor manufacturing. The cluster tool comprises a first transfer chamber having a first transfer robot. The cluster tool further comprises a designated storage chamber and a transfer load lock attached to the first transfer chamber. The cluster tool further comprises a second transfer chamber connected to the first transfer chamber through a pair of via connector chambers, the second transfer chamber having a second transfer robot. The cluster tool further comprises at least three epitaxial deposition chamber attached to the second transfer chamber. The cluster tool further comprises a control unit configured to control the second transfer robot to transfer wafers between the designated storage chamber and the transfer load lock.

Abstract: The present disclosure relates to an improved method of forming interconnection layers to reduce voids and improve reliability, and an associated device. In some embodiments, a dielectric layer is formed over a semiconductor substrate having an opening arranged within the dielectric layer. A metal seed layer is formed on the surfaces of the opening using a chemical vapor deposition (CVD) process. Then a metal layer is plated onto the metal seed layer to fill the opening. Forming the metal seed layer using a CVD process provides the seed layer with a good uniformity, which allows for high aspect ratio openings in the dielectric layer to be filled without voids or pinch off.

Abstract: Some embodiments relate to a method of manufacturing an integrated circuit device. In this method a dielectric layer is formed over a substrate. The dielectric layer comprises an opening arranged within the dielectric layer. A first cobalt liner is formed along bottom and sidewall surfaces of the opening. A barrier liner is formed on exposed surfaces of the first cobalt liner. A bulk cobalt layer is formed in the opening and over the barrier liner to fill a remaining space of the opening.

Abstract: A device includes a pedestal. The pedestal includes a ground electrode, a central portion, and a peripheral portion. The ground electrode includes a top surface from which the peripheral portion is projected, thereby having a height difference between the central portion and the peripheral portion.

Abstract: Cryogenic pump apparatuses include nanostructure material to achieve an ultra-high vacuum level. The nanostructure material can be mixed with either an adsorbent material or a fixed glue layer which is utilized to fix the adsorbent material. The nanostructure material's good thermal conductivity and adsorption properties help to lower working temperature and extend regeneration cycle of the cryogenic pumps.

Abstract: Among other things, one or more systems and techniques for promoting metal plating profile uniformity are provided. A magnetic structure is positioned relative to a semiconductor wafer that is to be electroplated with metal during a metal plating process. In an embodiment, the magnetic structure applies a force that decreases an edge plating current by moving metal ions away from a wafer edge of the semiconductor wafer. In an embodiment, the magnetic structure applies a force that increases a center plating current by moving metal ions towards a center portion of the semiconductor wafer. In this way, the edge plating current has a current value that is similar to a current value of the center plating current. The similarity between the center plating current and the edge plating current promotes metal plating uniformity.

Abstract: Among other things, one or more systems and techniques for promoting metal plating uniformity are provided. An insulator plate is positioned relative to a semiconductor wafer that is to be electroplated with metal during a metal plating process. The insulator plate comprises an insulator ring that provides a resistance to electrical plating current passing through the insulator ring to the semiconductor wafer. The insulator plate comprises one or more porous regions, such as holes, that introduce little to no additional resistance to electrical plating current passing through such porous regions to the semiconductor wafer. The insulator plate influences electrical plating current so that edge plating current has a current value similar to a center plating current. The similarity in plating current promotes metal plating uniformity for the semiconductor wafer.

Abstract: Methods of lining and/or filling gaps on a substrate by creating flowable silicon oxide-containing films are provided. The methods involve introducing vapor-phase silicon-containing precursor and oxidant reactants into a reaction chamber containing the substrate under conditions such that a condensed flowable film is formed on the substrate. The flowable film at least partially fills gaps on the substrates and is then converted into a silicon oxide film. In certain embodiments, the methods involve using a catalyst, e.g., a nucleophile or onium catalyst, in the formation of the film. The catalyst may be incorporated into one of the reactants and/or introduced as a separate reactant. Also provided are methods of converting the flowable film to a solid dielectric film. The methods of this invention may be used to line or fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.

Abstract: Multi-cycle methods result in dense, seamless and void-free dielectric gap fill are provided. The methods involve forming liquid or flowable films that partially fill a gap, followed by a solidification and/or anneal process that uniformly densifies the just-formed film. The thickness of the layer formed is such that the subsequent anneal process creates a film that does not have a density gradient. The process is then repeated as necessary to wholly or partially fill or line the gap as desired. The methods of this invention may be used to line or fill high aspect ratio gaps, including gaps having aspect ratios greater than about 6:1 with widths less than about 0.13 ?m.

Abstract: Methods of lining and/or filling gaps on a substrate by creating flowable silicon oxide-containing films are provided. The methods involve introducing vapor-phase silicon-containing precursor and oxidant reactants into a reaction chamber containing the substrate under conditions such that a condensed flowable film is formed on the substrate. The flowable film at least partially fills gaps on the substrates and is then converted into a silicon oxide film. In certain embodiments, the methods involve using a catalyst, e.g., a nucleophile or onium catalyst, in the formation of the film. The catalyst may be incorporated into one of the reactants and/or introduced as a separate reactant. Also provided are methods of converting the flowable film to a solid dielectric film. The methods of this invention may be used to line or fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.

Abstract: The invention relates to the production of nanoporous silica dielectric films and to semiconductor devices and integrated circuits comprising these improved films. The nanoporous films of the invention are prepared using silicon containing pre-polymers and are prepared by a process that allows crosslinking at lowered gel temperatures by means of a metal-ion-free onium or nucleophile catalyst.

Abstract: The invention relates to the production of nanoporous silica dielectric films and to semiconductor devices and integrated circuits comprising these improved films. The nanoporous films of the invention are prepared using silicon containing pre-polymers and are prepared by a process that allows crosslinking at lowered gel temperatures by means of a metal-ion-free onium or nucleophile catalyst.