Abstract: A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

Abstract: A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

Abstract: Techniques are disclosed relating to dual-edge triggered (DET) clock gater circuitry. In some embodiments, an apparatus includes a first series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry. In some embodiments, ones of the DET clock gater circuits are controlled by respective control signals and are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock. In some embodiments, the apparatus also includes a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

Abstract: The embodiments described herein relate to dynamically detecting a frequency change condition for microprocessor performance. An instruction is received, and a frequency change condition associated with the received instruction is dynamically detected. A frequency modulation is performed in response to the dynamic detection. The frequency modulation includes selecting a second frequency for optimal instruction processing different from a first frequency, the first frequency being a default operating frequency of the microprocessor. Execution of the instruction is completed at the second frequency. Accordingly, incoming execution instructions are logically analyzed, and the processor frequency is selectively modified based on associated instruction conditions.

Abstract: A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory, where the memory includes a program configured to adjust a frequency of a multi-core processor. The operations include determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The operations also include calculating a switching current by subtracting the leakage current from the total current and calculating an effective switching capacitance based at least in part on the switching current. The operations also include calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.

Abstract: A method and apparatus for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for the inhibited processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

Abstract: A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited and non-idle processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for both the inhibited and the non-idle processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

Abstract: Embodiments of the present disclosure relate to a flip flop circuit that obviates the need of a transmission gate. The flip flop includes a first match multiplexer, a second match multiplexer and a separable inverter. The first match multiplexer receives an input data signal and generates a feedback output based on the input data signal and the logic levels at two nodes coupled to the first match multiplexer. The separable inverter receives the feedback output and switches the logic level of one of two nodes but maintains the logic level per each clock cycle. The second match multiplexer generates a signal output based on the logic levels at the two nodes and the signal output that is fed back into the second match multiplexer. Embodiments may reduce power consumption and operate at lower voltages.

Abstract: Techniques are disclosed relating to dual-edge triggered (DET) clock gater circuitry. In some embodiments, an apparatus includes a first series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry. In some embodiments, ones of the DET clock gater circuits are controlled by respective control signals and are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock. In some embodiments, the apparatus also includes a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.

Abstract: Techniques are disclosed relating to generating an overdrive voltage for power switch circuitry. In some embodiments, the value of the overdrive voltage is adjusted dynamically in order to reduce leakage current during power gating. In some embodiments, an apparatus includes a power switch circuit element configured to gate power to circuitry in the apparatus based on a control signal. In some embodiments, the power switch circuit element is powered by a supply voltage. In some embodiments, the apparatus also includes control circuitry configured to generate the control voltage at a different voltage level than the supply voltage, based on comparison of leakage current of ones of a plurality of replicas of the power switch circuit element. In some embodiments, the replicas are configured to receive different reference voltages as respective replica control signals. In various embodiments, the disclosed techniques may generate overdrive voltages that reduce leakage current during power gating.

Abstract: A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The method also includes calculating a switching current by subtracting the leakage current from the total current. The method also includes calculating an effective switching capacitance based at least in part on the switching current. The method also includes calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.

Abstract: Embodiments of the present disclosure relate to a flip flop circuit that obviates the need of a transmission gate. The flip flop includes a first match multiplexer, a second match multiplexer and a separable inverter. The first match multiplexer receives an input data signal and generates a feedback output based on the input data signal and the logic levels at two nodes coupled to the first match multiplexer. The separable inverter receives the feedback output and switches the logic level of one of two nodes but maintains the logic level per each clock cycle. The second match multiplexer generates a signal output based on the logic levels at the two nodes and the signal output that is fed back into the second match multiplexer. Embodiments may reduce power consumption and operate at lower voltages.

Abstract: Embodiments relate to modulating a power supply voltage for varying a propagation delay of data paths within an integrated circuit. The power supply voltage is modulated to increase the delay of shorter data paths for reducing an incidence of hold time violations without substantially affecting the delay of longer data paths. For example, the power supply voltage is reduced from a nominal value in the first half clock cycle to increase delay of both the shorter data paths and the longer data paths. The power supply voltage is increased from the nominal value in the second half clock cycle to decrease delay of the longer data paths within the second half clock cycle such that the overall delay of the longer data paths is virtually same as when the power supply voltage is fixed at the nominal value for the entire clock cycle.

Abstract: The embodiments described herein relate to dynamically detecting a frequency change condition for microprocessor performance. An instruction is received, and a frequency change condition associated with the received instruction is dynamically detected. A frequency modulation is performed in response to the dynamic detection. The frequency modulation includes selecting a second frequency for optimal instruction processing different from a first frequency, the first frequency being a default operating frequency of the microprocessor. Execution of the instruction is completed at the second frequency. Accordingly, incoming execution instructions are logically analyzed, and the processor frequency is selectively modified based on associated instruction conditions.

Abstract: Embodiments relate to modulating a power supply voltage for varying a propagation delay of data paths within an integrated circuit. The power supply voltage is modulated to increase the delay of shorter data paths for reducing an incidence of hold time violations without substantially affecting the delay of longer data paths. For example, the power supply voltage is reduced from a nominal value in the first half clock cycle to increase delay of both the shorter data paths and the longer data paths. The power supply voltage is increased from the nominal value in the second half clock cycle to decrease delay of the longer data paths within the second half clock cycle such that the overall delay of the longer data paths is virtually same as when the power supply voltage is fixed at the nominal value for the entire clock cycle.

Abstract: Techniques are disclosed relating to dual-edge triggered clock gater circuitry. In some embodiments, an apparatus includes dual-edge triggered clock gater circuitry configured to generate an output signal based on an input clock signal and a control signal that indicates whether to gate the input clock signal. In some embodiments, the clock gater circuitry includes first and second storage elements. In some embodiments, the clock gater circuitry includes multiplexer circuitry that selects between outputs of the first and second storage elements to generate the output signal. In some embodiments, the clock gater circuitry includes a third storage element configured to store an indication of which of the first and second storage elements stores a first digital value and which stores an inverse of the first digital value when not gating.

Abstract: A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory. The memory stores program code, which, when executed on the processor, performs an operation for adjusting a frequency of a processor. The operation includes inhibiting one or more processor cores from exiting an idle state. The operation further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The operation also includes selecting a maximum frequency for the inhibited and non-idle processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The operation includes setting the maximum frequency for both the inhibited and the non-idle processor cores, and then uninhibiting the processor cores requesting exit from the idle state.