Patents by Inventor Vidyabhushan Mohan
Vidyabhushan Mohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230229552Abstract: An indication is received from a storage device that an attempt to read a portion of data from a block of the storage device has failed. A command is transmitted to the storage device to perform a scan on data stored at the block comprising the portion of data to acquire failure information associated with a plurality of subsets of the data stored at the block. The failure information associated with the plurality of subsets of the data stored at the block is received from the storage device.Type: ApplicationFiled: February 24, 2023Publication date: July 20, 2023Inventors: DAMIAN YURZOLA, VIDYABHUSHAN MOHAN, GORDON JAMES COLEMAN, MELISSA KIMBLE, HARI KANNAN
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Patent number: 11656961Abstract: Failure information associated with a plurality of blocks of a solid-state storage device of a plurality of solid-state storage devices is received. One or more blocks of the plurality of blocks storing uncorrectable data are identified based on the received failure information. A partial deallocation of the one or more blocks of the plurality of blocks is issued, the partial deallocation indicating that the one or more blocks store uncorrectable data. A remedial action associated with the one or more blocks of the plurality of blocks is performed.Type: GrantFiled: November 12, 2021Date of Patent: May 23, 2023Assignee: PURE STORAGE, INC.Inventors: Damian Yurzola, Gordon James Coleman, Vidyabhushan Mohan, Melissa Kimble
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Patent number: 11604690Abstract: An indication is received from a storage device that an attempt to read a portion of data from a block of the storage device has failed. A command is transmitted to the storage device to perform a scan on data stored at the block comprising the portion of data to acquire failure information associated with a plurality of subsets of the data stored at the block. The failure information associated with the plurality of subsets of the data stored at the block is received from the storage device.Type: GrantFiled: December 13, 2019Date of Patent: March 14, 2023Assignee: PURE STORAGE, INC.Inventors: Damian Yurzola, Vidyabhushan Mohan, Gordon James Coleman, Melissa Kimble, Hari Kannan
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Patent number: 11538539Abstract: Systems and methods for solid-state storage drive-level failure prediction and health metric are described. A plurality of host-write commands are received at a solid-state storage device. A number of drive-writes per day based on the on the plurality of host-write commands is determined. An aggregated amount of degradation to one or more internal non-volatile memory components based on the number of drive-writes per day is determined. Using a machine-learned model, a probability of failure value based on a set of parameter data and the aggregated amount of degradation to the non-volatile memory component is generated. An alert is generated, based on the probability of failure value or degradation threshold.Type: GrantFiled: July 14, 2020Date of Patent: December 27, 2022Assignee: Western Digital Technologies, Inc.Inventors: Jay Sarkar, Cory Peterson, Amir Sanayei, Vidyabhushan Mohan, Yao Zhang
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Publication number: 20220075699Abstract: Failure information associated with a plurality of blocks of a solid-state storage device of a plurality of solid-state storage devices is received. One or more blocks of the plurality of blocks storing uncorrectable data are identified based on the received failure information. A partial deallocation of the one or more blocks of the plurality of blocks is issued, the partial deallocation indicating that the one or more blocks store uncorrectable data. A remedial action associated with the one or more blocks of the plurality of blocks is performed.Type: ApplicationFiled: November 12, 2021Publication date: March 10, 2022Inventors: Damian Yurzola, Gordon James Coleman, Vidyabhushan Mohan, Melissa Kimble
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Patent number: 11188432Abstract: Failure information associated with a plurality of blocks of a solid-state storage device of a plurality of solid-state storage devices is received. One or more blocks of the plurality of blocks storing uncorrectable data are identified based on the received failure information. A partial deallocation of the one or more blocks of the plurality of blocks is issued, the partial deallocation indicating that the one or more blocks store uncorrectable data. A remedial action associated with the one or more blocks of the plurality of blocks is performed.Type: GrantFiled: February 28, 2020Date of Patent: November 30, 2021Assignee: Pure Storage, Inc.Inventors: Damian Yurzola, Gordon James Coleman, Vidyabhushan Mohan, Melissa Kimble
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Publication number: 20210271578Abstract: Failure information associated with a plurality of blocks of a solid-state storage device of a plurality of solid-state storage devices is received. One or more blocks of the plurality of blocks storing uncorrectable data are identified based on the received failure information. A partial deallocation of the one or more blocks of the plurality of blocks is issued, the partial deallocation indicating that the one or more blocks store uncorrectable data. A remedial action associated with the one or more blocks of the plurality of blocks is performed.Type: ApplicationFiled: February 28, 2020Publication date: September 2, 2021Inventors: Damian Yurzola, Gordon James Coleman, Vidyabhushan Mohan, Melissa Kimble
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Publication number: 20200342945Abstract: Systems and methods for solid-state storage drive-level failure prediction and health metric are described. A plurality of host-write commands are received at a solid-state storage device. A number of drive-writes per day based on the on the plurality of host-write commands is determined. An aggregated amount of degradation to one or more internal non-volatile memory components based on the number of drive-writes per day is determined. Using a machine-learned model, a probability of failure value based on a set of parameter data and the aggregated amount of degradation to the non-volatile memory component is generated. An alert is generated, based on the probability of failure value or degradation threshold.Type: ApplicationFiled: July 14, 2020Publication date: October 29, 2020Inventors: Jay SARKAR, Cory PETERSON, Amir SANAYEI, Vidyabhushan MOHAN, Yao ZHANG
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Patent number: 10726930Abstract: Systems and methods for solid-state storage drive-level failure prediction and health metric are described. A plurality of host-write commands are received at a solid-state storage device. A number of drive-writes per day based on the on the plurality of host-write commands is determined. An aggregated amount of degradation to one or more internal non-volatile memory components based on the number of drive-writes per day is determined. Using a machine-learned model, a probability of failure value based on a set of parameter data and the aggregated amount of degradation to the non-volatile memory component is generated. An alert is generated, based on the probability of failure value or degradation threshold.Type: GrantFiled: May 14, 2018Date of Patent: July 28, 2020Assignee: Western Digital Technologies, Inc.Inventors: Jay Sarkar, Cory Peterson, Amir Sanayei, Vidyabhushan Mohan, Yao Zhang
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Publication number: 20200117534Abstract: An indication is received from a storage device that an attempt to read a portion of data from a block of the storage device has failed. A command is transmitted to the storage device to perform a scan on data stored at the block comprising the portion of data to acquire failure information associated with a plurality of subsets of the data stored at the block. The failure information associated with the plurality of subsets of the data stored at the block is received from the storage device.Type: ApplicationFiled: December 13, 2019Publication date: April 16, 2020Inventors: Damian Yurzola, Vidyabhushan Mohan, Gordon James Coleman, Melissa Kimble, Hari Kannan
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Patent number: 10459644Abstract: A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die, a local memory connected to (or part of) the controller and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations. When the memory system receives instructions to use the compute engine to perform data manipulation operations, the local memory is reallocated such that an amount of space allocated in the local memory for logical to physical translation information is changed based on the one or more data manipulation instructions.Type: GrantFiled: October 6, 2017Date of Patent: October 29, 2019Assignee: Western Digital Techologies, Inc.Inventors: Pankaj Mehra, Vidyabhushan Mohan
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Patent number: 10387303Abstract: A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations.Type: GrantFiled: August 9, 2017Date of Patent: August 20, 2019Assignee: Western Digital Technologies, Inc.Inventors: Pankaj Mehra, Vidyabhushan Mohan, Seung-Hwan Song, Dejan Vucinic, Chao Sun, Minghai Qin, Arup De
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Publication number: 20190108888Abstract: Systems and methods for solid-state storage drive-level failure prediction and health metric are described. A plurality of host-write commands are received at a solid-state storage device. A number of drive-writes per day based on the on the plurality of host-write commands is determined. An aggregated amount of degradation to one or more internal non-volatile memory components based on the number of drive-writes per day is determined. Using a machine-learned model, a probability of failure value based on a set of parameter data and the aggregated amount of degradation to the non-volatile memory component is generated. An alert is generated, based on the probability of failure value or degradation threshold.Type: ApplicationFiled: May 14, 2018Publication date: April 11, 2019Inventors: Jay SARKAR, Cory PETERSON, Amir SANAYEI, Vidyabhushan MOHAN, Yao ZHANG
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Publication number: 20180121121Abstract: A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die, a local memory connected to (or part of) the controller and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations. When the memory system receives instructions to use the compute engine to perform data manipulation operations, the local memory is reallocated such that an amount of space allocated in the local memory for logical to physical translation information is changed based on the one or more data manipulation instructions.Type: ApplicationFiled: October 6, 2017Publication date: May 3, 2018Applicant: Western Digital Technologies, Inc.Inventors: Pankaj Mehra, Vidyabhushan Mohan
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Patent number: 9959078Abstract: Systems and methods for increasing performance and reducing power consumption of a non-volatile memory system while the system acquires status information from a plurality of memory die are described. The non-volatile memory system may include a plurality of memory die and a system controller for controlling operations performed by each memory die of the plurality of memory die (e.g., read operations, write operations, or erase operations). The system controller may transmit or broadcast a first status command to each memory die of the plurality of memory die and in response simultaneously or concurrently receive one or more sets of status information from each memory die of the plurality of memory die. The status information may include ready/busy status information (e.g., indicating that a memory die is able to receive new data), programming loop count information, and erase loop count information.Type: GrantFiled: October 30, 2015Date of Patent: May 1, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Grishma Shah, Jack Frayer, Aaron Olbrich, Chang Siau, Vidyabhushan Mohan, Gopinath Balakrishnan, Robert Ellis
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Publication number: 20180052766Abstract: A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations.Type: ApplicationFiled: August 9, 2017Publication date: February 22, 2018Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Pankaj Mehra, Vidyabhushan Mohan, Seung-Hwan Song, Dejan Vucinic, Chao Sun, Minghai Qin, Arup De
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Patent number: 9864545Abstract: Systems, methods, and/or devices are used to automate read operations performed at an open erase block. In one aspect, the method includes: receiving a read command, at a storage device, to read data from non-volatile memory of the storage device. In response to receiving the read command, the method further includes: 1) reading data using a first set of memory operation parameters in response to a determination that the read command is not for reading data from a predefined portion of an open erase block (e.g., an erase block that is determined to be an open erase block) of the non-volatile memory and 2) reading data using a second set of memory operation parameters (i.e., the second set is distinct from the first set) in response to a determination that the read command is for reading data from the predefined portion of an open erase block of the non-volatile memory.Type: GrantFiled: October 28, 2015Date of Patent: January 9, 2018Assignee: SanDisk Technologies LLCInventors: Robert W. Ellis, Vidyabhushan Mohan, Jack Edward Frayer
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Patent number: 9753653Abstract: Systems, methods, and/or devices are used to manage high-priority NAND operations. In some embodiments, the method includes receiving a first command (e.g., requesting a high-priority memory operation) corresponding to a first location (e.g., having both a first physical address and a first aliased physical address) in a first die of a plurality of physical non-volatile memory die in a storage device. If the first die is performing a blocking low-priority memory operation (e.g., the low-priority operation was sent to the first die using a second physical address), the method includes sending a memory operation command, corresponding to the first memory operation, to the first die using the first aliased physical address. In some embodiments, a predefined die-selection portion of the second physical address matches the predefined die-selection portion of the first physical address and does not match the predefined die-selection portion of the first aliased physical address.Type: GrantFiled: October 28, 2015Date of Patent: September 5, 2017Assignee: SanDisk Technologies LLCInventors: Robert W. Ellis, Jack Edward Frayer, Vidyabhushan Mohan, Todd Lindberg
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Publication number: 20170147499Abstract: In a method to provide scalable and distributed address mapping in a storage device, a host command that specifies an operation to be performed and a logical address corresponding to a portion of memory within the storage device is received or accessed. A storage controller of the storage device maps the specified logical address to a first subset of a physical address, using a first address translation table, and identifies an NVM module of the plurality of NVM modules, in accordance with the first subset of a physical address. The method further includes, at the identified NVM module, mapping the specified logical address to a second subset of the physical address, using a second address translation table, identifying the portion of non-volatile memory within the identified NVM module corresponding to the specified logical address, and executing the specified operation on the portion of memory in the identified NVM module.Type: ApplicationFiled: June 10, 2016Publication date: May 25, 2017Inventors: Vidyabhushan Mohan, Jack Edward Frayer
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Patent number: 9653184Abstract: The various embodiments described herein include systems, methods and/or devices used to enable physical-to-physical address remapping in a storage module. In one aspect, the method includes, for each of a sequence of two or more units of non-volatile memory, determining a validity state of a respective unit of memory. In accordance with a determination that the validity state of the respective unit of memory is an invalid state, the method includes storing, in a table, a second address assigned to the respective unit of memory. At least a portion of the second address is a physical address portion corresponding to a physical location of a second unit of memory. In accordance with a determination that the validity state of the respective unit of memory is a valid state, the method includes forgoing assignment of the second address corresponding to the unit of memory.Type: GrantFiled: January 14, 2015Date of Patent: May 16, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Jack Edward Frayer, Vidyabhushan Mohan