Abstract: The various embodiments described herein include systems, methods and/or devices used to package non-volatile memory. In one aspect, the method includes: (1) selecting, from a set of non-volatile memory die, a plurality of non-volatile memory die on which one or more tests have been deferred until after packaging, the selecting in accordance with wafer positions of the plurality of non-volatile memory die and statistical die performance information corresponding to the wafer positions; and (2) packaging the selected plurality of non-volatile memory die. In some embodiments, after said packaging, the method further includes performing a set of tests on the plurality of non-volatile memory die to identify respective units of memory within the plurality of non-volatile memory die that meet predefined validity criteria, wherein the set of tests performed include at least one of the deferred one or more tests.

Abstract: A memory address and a virtual cache identifier are received in association with a request to retrieve data from a cache data array. Context information is selected based on the virtual cache identifier, the context information indicating a first region of a plurality of regions within the cache data array. A cache line address that includes a first number of bits of the memory address in accordance with a size of the first region is generated and, if the cache data array is determined to contain, in a location indicated by the cache line address, a cache line corresponding to the memory address, the cache line is retrieved from the location indicated by the cache line address.

Abstract: Systems, methods, and/or devices are used to manage high-priority NAND operations. In some embodiments, the method includes receiving a first command (e.g., requesting a high-priority memory operation) corresponding to a first location (e.g., having both a first physical address and a first aliased physical address) in a first die of a plurality of physical non-volatile memory die in a storage device. If the first die is performing a blocking low-priority memory operation (e.g., the low-priority operation was sent to the first die using a second physical address), the method includes sending a memory operation command, corresponding to the first memory operation, to the first die using the first aliased physical address. In some embodiments, a predefined die-selection portion of the second physical address matches the predefined die-selection portion of the first physical address and does not match the predefined die-selection portion of the first aliased physical address.

Abstract: Systems, methods, and/or devices are used to automate read operations performed at an open erase block. In one aspect, the method includes: receiving a read command, at a storage device, to read data from non-volatile memory of the storage device. In response to receiving the read command, the method further includes: 1) reading data using a first set of memory operation parameters in response to a determination that the read command is not for reading data from a predefined portion of an open erase block (e.g., an erase block that is determined to be an open erase block) of the non-volatile memory and 2) reading data using a second set of memory operation parameters (i.e., the second set is distinct from the first set) in response to a determination that the read command is for reading data from the predefined portion of an open erase block of the non-volatile memory.

Abstract: In a method to perform garbage collection in storage device having a plurality of non-volatile memory (NVM) modules that each include two or more non-volatile memory includes, at a storage controller for the storage device, using status information locally stored in the storage controller with respect to individual NVM modules or individual non-volatile memory devices in the storage device, identifying an NVM module or non-volatile memory device, and sending a garbage collection command to a selected NVM module. The selected NVM module, in accordance with the garbage collection command and status information locally stored in the selected NVM module, selects a memory portion of non-volatile memory in the selected module and initiates garbage collection of valid data in the selected memory portion, which includes copying valid data in the selected memory portion to a target memory portion in the selected module.

Abstract: Systems and methods for increasing performance and reducing power consumption of a non-volatile memory system while the system acquires status information from a plurality of memory die are described. The non-volatile memory system may include a plurality of memory die and a system controller for controlling operations performed by each memory die of the plurality of memory die (e.g., read operations, write operations, or erase operations). The system controller may transmit or broadcast a first status command to each memory die of the plurality of memory die and in response simultaneously or concurrently receive one or more sets of status information from each memory die of the plurality of memory die. The status information may include ready/busy status information (e.g., indicating that a memory die is able to receive new data), programming loop count information, and erase loop count information.

Abstract: The various implementations described herein include systems, methods and/or devices used to perform a method of reliability management of data in a storage device having a plurality of memory modules. The method includes receiving or accessing a host command to perform a specified operation on a portion of non-volatile memory within a storage device. The method also includes, at a storage controller for the storage device, identifying a module of the plurality of modules, in accordance with the host command. The method includes, at the identified module, retrieving health information for the portion of non-volatile memory within the identified module, modifying one or more memory operation parameters in accordance with the specified operation and the retrieved health information, and executing the specified operation on the portion of non-volatile memory in the identified module in accordance with the one or more modified memory operation parameters.

Abstract: In a method to provide scalable and distributed address mapping in a storage device, a host command that specifies an operation to be performed and a logical address corresponding to a portion of memory within the storage device is received or accessed. A storage controller of the storage device maps the specified logical address to a first subset of a physical address, using a first address translation table, and identifies an NVM module of the plurality of NVM modules, in accordance with the first subset of a physical address. The method further includes, at the identified NVM module, mapping the specified logical address to a second subset of the physical address, using a second address translation table, identifying the portion of non-volatile memory within the identified NVM module corresponding to the specified logical address, and executing the specified operation on the portion of memory in the identified NVM module.

Abstract: The various embodiments described herein include systems, methods and/or devices used to enable physical-to-physical address remapping in a storage module. In one aspect, the method includes, for each of a sequence of two or more units of non-volatile memory, determining a validity state of a respective unit of memory. In accordance with a determination that the validity state of the respective unit of memory is an invalid state, the method includes storing, in a table, a second address assigned to the respective unit of memory. At least a portion of the second address is a physical address portion corresponding to a physical location of a second unit of memory. In accordance with a determination that the validity state of the respective unit of memory is a valid state, the method includes forgoing assignment of the second address corresponding to the unit of memory.

Abstract: The various embodiments described herein include systems, methods and/or devices used to package non-volatile memory. In one aspect, the method includes: (1) selecting, from a set of non-volatile memory die, a plurality of non-volatile memory die on which one or more tests have been deferred until after packaging, the selecting in accordance with wafer positions of the plurality of non-volatile memory die and statistical die performance information corresponding to the wafer positions; and (2) packaging the selected plurality of non-volatile memory die. In some embodiments, after said packaging, the method further includes performing a set of tests on the plurality of non-volatile memory die to identify respective units of memory within the plurality of non-volatile memory die that meet predefined validity criteria, wherein the set of tests performed include at least one of the deferred one or more tests.

Abstract: The embodiments described herein are used to execute staggered memory operations. The method includes, at each of a plurality of distinct memory portions of the storage device, establishing a non-zero command delay parameter distinct from a command delay parameter established for one or more of the other memory portions in the plurality of distinct memory portions. The method further includes, after establishing the non-zero command delay parameter in each of the plurality of distinct memory portions of the storage device, executing memory operations in two or more of the plurality of distinct memory portions of the storage device during overlapping time periods, the executing including, in each memory portion of the plurality of memory portions, delaying execution of a respective memory operation by an amount of time corresponding to the command delay parameter established for that memory portion.

Abstract: The various embodiments described herein include systems, methods and/or devices used to packaging non-volatile memory. In one aspect, the method includes, selecting, from a set of non-volatile memory die, a plurality of non-volatile memory die on which predefined die-level and sub-die level tests have been deferred until after packaging, in accordance with predefined criteria and predefined statistical die performance information corresponding to the set of non-volatile memory die. The method further includes packaging the selected plurality of non-volatile memory die into a memory device. After said packaging, the method further includes performing a set of tests on the plurality of non-volatile memory die in the memory device to identify respective units of memory within the non-volatile memory die in the memory device that meet predefined validity criteria, wherein the set of tests performed include the deferred predefined die-level and sub-die level tests.