Patents by Inventor Viet Nguyen Hoang

Viet Nguyen Hoang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120001570
    Abstract: A method is disclosed of controlling a LED, comprising driving the LED with a DC current for a first time, interrupting the DC current for a second time such that the first time and the second time sum to a period, determining at least one characteristic of the LED whilst the DC current is interrupted, and controlling the DC current during a subsequent period in dependence on the at least one characteristic. The invention thus benefits from the simplicity of DC operation. By operating at the LED in a DC mode, rather than say in a PWM mode, the requirement to be able to adjust the duty cycle is avoided. By including interruptions to the DC current, it is possible to utilise the LED itself to act as a sensor in order to determine a characteristic of the LED. The need for additional sensors is thereby avoided.
    Type: Application
    Filed: February 25, 2010
    Publication date: January 5, 2012
    Applicant: NXP B.V.
    Inventors: Peter Hubertus Franciscus Deurenberg, Gert-Jan Koolen, Gian Hoogzaad, Radu Surdeanu, Pascal Bancken, Benoit Bataillou, Viet Nguyen Hoang
  • Patent number: 8012872
    Abstract: Manufacturing a damascene structure involves: forming a sacrificial layer (20) on a substrate (10) to protect an area around a recess (30) for the damascene structure, forming a barrier layer (40) in the recess, and in electrical contact with the sacrificial layer, forming the damascene structure (50) in the recess, and planarizing. During the planarizing the sacrificial layer reacts electrochemically with the barrier layer or with the damascene structure. This can alter a relative rate of removal of the damascene structure and the sacrificial layer so as to reduce dishing or protrusion of the damascene structure, and reduce copper residues, and reduce barrier corrosion. The barrier layer can be formed by ALCVD. The barrier material being one or more of WCN and TaN. The sacrificial layer can be TaN, TiN or W.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: September 6, 2011
    Assignee: NXP B.V.
    Inventors: Viet Nguyen Hoang, Greja J. A. M. Verheijden
  • Patent number: 7985673
    Abstract: The invention relates to a semiconductor device manufactured in a process technology, the semiconductor device having at least one wire located in an interconnect layer of said semiconductor device, the at least one wire having a wire width (W) and a wire thickness (T), the wire width (W) being equal to a minimum feature size of the interconnect layer as defined by said process technology, wherein the minimum feature size is smaller than or equal to 0.32 ?m, wherein the aspect ratio (AR) of the at least one wire is smaller than 1.5, the aspect ratio (AR) being defined as the wire thickness (T) divided by the wire width (W). The invention further discloses a method of manufacturing such a semiconductor device.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: July 26, 2011
    Assignee: NXP B.V.
    Inventors: Viet Nguyen Hoang, Phillip Christie, Julien M. M. Michelon
  • Publication number: 20110147944
    Abstract: Manufacturing a damascene structure involves: forming a sacrificial layer (20) on a substrate (10) to protect an area around a recess (30) for the damascene structure, forming a barrier layer (40) in the recess, and in electrical contact with the sacrificial layer, forming the damascene structure (50) in the recess, and planarising. During the planarising the sacrificial layer reacts electrochemically with the barrier layer or with the damascene structure. This can alter a relative rate of removal of the damascene structure and the sacrificial layer so as to reduce dishing or protrusion of the damascene structure, and reduce copper residues, and reduce barrier corrosion. The barrier layer can be formed by ALCVD. The barrier material being one or more of WCN and TaN. The sacrificial layer can be TaN, TiN or W.
    Type: Application
    Filed: November 2, 2005
    Publication date: June 23, 2011
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Viet Nguyen Hoang, Greja Johanna Adriana Maria Verheijden
  • Publication number: 20110150028
    Abstract: The present invention relates to a calibration circuit, computer program product, and method of calibrating a junction temperature measurement of a semiconductor element, wherein respective forward voltages at junctions of the semiconductor element and a reference temperature sensor are measured, and an absolute ambient temperature is determined by using the reference temperature sensor, and the junction temperature of the semiconductor element is predicted based on the absolute ambient temperature and the measured forward voltages.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 23, 2011
    Applicant: NXP B.V.
    Inventors: Viet NGUYEN HOANG, Pascal BANCKEN, Radu SURDEANU, Benoit BATAILLOU, David van STEENWINCKEL
  • Publication number: 20110133214
    Abstract: A light sensor device comprises a substrate (10) having a well (12) defined in one surface. At least one light sensor (14) is formed at the base of the well (12), and an optical light guide (18) in the form of a transparent tunnel (18) within an opaque body (20) extends from a top surface of the device down a sloped side wall of the well (12) to the location of the light sensor (14).
    Type: Application
    Filed: May 21, 2009
    Publication date: June 9, 2011
    Applicant: NXP B.V.
    Inventors: Viet Nguyen Hoang, Radu Surdeanu, Pascal Bancken, Benoit Bataillou, David Van Steenwinckel
  • Publication number: 20110121705
    Abstract: Apparatus for regulating the temperature of a light emitting diode (LED). The apparatus includes a heat sink, an LED mount, and an LED mounted on the LED mount. The LED mount is configured to change shape in response to a change in temperature. The change in shape alters the position of the LED relative to the heat sink, for adjusting heat transfer between the LED and the heat sink. The LED mount may include a laminated portion such as a bi-metallic strip.
    Type: Application
    Filed: October 22, 2010
    Publication date: May 26, 2011
    Applicant: NXP B.V.
    Inventors: Pascal BANCKEN, Viet NGUYEN HOANG, Radu SURDEANU, Benoit BATAILLOU, David van STEENWINCKEL
  • Publication number: 20110109897
    Abstract: An apparatus comprising at least one measuring cell (10) is disclosed. The measuring cell comprises a first cavity (16 and a second cavity (18) perpendicular to the first cavity, the first cavity and the second cavity comprising an overlap at first respective ends and a reflective surface (20) at the opposite respective ends. A beam splitter (15) is located in the overlap and an electromagnetic radiation source (12) is arranged to project a beam of electromagnetic radiation onto the beam splitter (15) such that the beam is projected into each of the cavities. A phase detector (22) for detecting a phase difference between the respective electromagnetic radiation reflected by the first and second cavity (16; 18) is also provided. In addition, the apparatus has a fluid channel (26), at least a part of which runs parallel to the first cavity (16) such that the electromagnetic radiation projected into the first cavity extends into said part of the fluid channel.
    Type: Application
    Filed: July 1, 2009
    Publication date: May 12, 2011
    Applicant: NXP B.V.
    Inventors: Benoit Bataillou, Pascal Bancken, David van Steenwinckel, Viet Nguyen Hoang, Radu Surdeanu
  • Publication number: 20110103039
    Abstract: The present invention relates to a luminescent component (30) and a manufacturing method thereof. The luminescent component (30) comprises a first transparent carrier (18), a second transparent carrier (24), a substrate (10) sandwiched between said transparent carriers (18; 24), the substrate (10) comprising a conduit from the first transparent layer (18) to the second transparent carrier (24), the conduit being filled with a luminescent solution (20). This facilitates the use of colloidal solutions of quantum dots in such a luminescent component (30). Preferably, the substrate (10) is direct bonded to the transparent carriers (18, 24) using direct wafer bonding techniques.
    Type: Application
    Filed: March 9, 2009
    Publication date: May 5, 2011
    Applicant: NXP B.V.
    Inventors: Viet Nguyen Hoang, Radu Surdeanu, Benoit Bataillou
  • Publication number: 20110097896
    Abstract: The present invention relates to a method for fabrication of in-laid metal interconnects. The method comprises the steps of providing a substrate with a dielectric material (1) on top thereof, depositing a protection layer (2) on top of the dielectric material, depositing a sacrificial layer (7) on top of the protection layer, the sacrificial layer having a mechanical strength that is lower than the mechanical strength of the protection layer, making an opening (3) through the sacrificial layer, through the protection layer and into the dielectric material, depositing a barrier layer (4) in the opening and on the sacrificial layer, depositing metal material (5) on the barrier layer, the metal material filling the opening, removing portions of the metal material existing beyond the opening by means of polishing, and removing the barrier layer and the sacrificial layer in one polishing step.
    Type: Application
    Filed: August 4, 2003
    Publication date: April 28, 2011
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Roel Daamen, Viet Nguyen Hoang, Romano Hoofman, Greja Verheijoen
  • Patent number: 7927966
    Abstract: The invention relates to a method of manufacturing openings in a substrate (5), the method comprising steps of: providing the substrate (5) with a masking layer (40) on a surface thereof; forming a first opening (10), a second opening (30), and a channel (20) in between the first opening (10) and the second opening (30) in the masking layer (40), the channel (20) connecting the first opening (10) with the second opening (30), the second opening (30) having an area (A2) that is larger than the area (A1) of the first opening (10); forming trenches (11, 21, 31) in the substrate (5) located at the first opening (10), the second opening (30), and at the channel (20) under masking of the masking layer (40) by means of anisotropic dry etching, and sealing off the trench (21) located at the channel (20) for forming the openings in the substrate (5). The method of the invention enables formation of a deeper first opening (10) than what is possible with the known methods.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: April 19, 2011
    Assignee: NXP B.V.
    Inventors: Viet Nguyen Hoang, Martinus T. Bennebroek
  • Publication number: 20110084701
    Abstract: A method of determining the ageing characteristics of an LED comprises applying a current stress pulse to the LED. The LED is monitored to determine when the thermal heating induced by the current stress pulse has been dissipated to a desired level. The operational characteristics of the LED are then measured before applying the next stressing pulse. This method accelerates the effect of aging in a reproducible way and therefore is able to greatly reduce the time needed for a reliability test.
    Type: Application
    Filed: September 3, 2010
    Publication date: April 14, 2011
    Applicant: NXP B.V.
    Inventors: Pascal BANCKEN, Viet NGUYEN HOANG, Radu SURDEANU
  • Publication number: 20110080113
    Abstract: A method of estimating the output light flux of a light emitting diode, comprises applying a drive current waveform to the LED over a period of time comprising a testing period. The forward voltage across the LED is monitored during the testing period, and the output light flux is estimated as a function of changes in the forward voltage.
    Type: Application
    Filed: September 3, 2010
    Publication date: April 7, 2011
    Applicant: NXP B.V.
    Inventors: Viet NGUYEN HOANG, Pascal BANCKEN, Radu SURDEANU
  • Publication number: 20110037135
    Abstract: A method of providing a dielectric material (18) having regions (18?, 18?) with a varying thickness in an IC manufacturing process is disclosed. The method comprises forming a plurality of patterns in respective regions (20?, 20?) of the dielectric material (18), each pattern increasing the susceptibility of the dielectric material (18) to a dielectric material removal step by a predefined amount and exposing the dielectric material (18) to the dielectric material removal step.
    Type: Application
    Filed: April 14, 2009
    Publication date: February 17, 2011
    Applicant: NXP B.V.
    Inventors: Viet Nguyen Hoang, Radu Surdeanu, Benoit Bataillou
  • Publication number: 20110031903
    Abstract: A method of estimating the junction temperature of a light emitting diode comprises driving a forward bias current through the diode, the current comprising a square wave which toggles between high and low current values (Ihigh, llow), the high current value (lhigh) comprising an LED operation current, and the low current value (IIOW) comprising a non-zero measurement current. The forward bias voltage drop (Vf) is sampled and the forward bias voltage drop (Vflow) is determined at the measurement current (IIOW)—The temperature is derived from the determined forward bias voltage drop.
    Type: Application
    Filed: January 27, 2009
    Publication date: February 10, 2011
    Applicant: NXP B.V.
    Inventors: Viet Nguyen Hoang, Radu Surdeanu, Pascal Bracken, Benoit Bataillou, David Van Steenwinckel
  • Publication number: 20110012158
    Abstract: The present invention relates to a manufacturing method of an integrated circuit (IC) comprising a substrate (10) comprising a pixelated element (12) and a light path (38) to the pixelated element (12). The IC comprises a first dielectric layer (14) covering the substrate (10) but not the pixilated element (12), a first metal layer (16) covering a part of the first dielectric layer (14), a second dielectric layer (18) covering a further part of first dielectric layer (14), a second metal layer (20) covering a part of the second dielectric layer (18) and extending over the pixelated element (12) and a part of the first metal layer (16), the first metal layer (16) and the second metal layer (20) forming an air-filled light path (38) to the pixelated element (12).
    Type: Application
    Filed: March 9, 2009
    Publication date: January 20, 2011
    Applicant: NXP B.V.
    Inventors: Viet Nguyen Hoang, Radu Surdeanu, Benoit Bataillou
  • Publication number: 20110006328
    Abstract: A lighting unit comprises a packaging substrate (10) formed from a semiconductor, a channel (12) formed in the substrate and a discrete light emitting diode arrangement (34) in the channel. A surface region of the channel comprises doped semiconductor layers (20,24) which define a light sensor. The arrangement provides a light sensor (which can be used to determine colour and/or output flux) for a LED unit, with the light sensor embedded in substrate used for packaging. This provides a low cost integration process and provides good registration between the light sensor and the LED output.
    Type: Application
    Filed: January 27, 2009
    Publication date: January 13, 2011
    Applicant: NXP B.V.
    Inventors: Radu Surdeanu, Viet Nguyen Hoang, Benoit Bataillou
  • Publication number: 20100308833
    Abstract: A method of determining the dominant output wavelength of an LED, comprises determining an electrical characteristic of the LED which is dependent on the voltage-capacitance characteristics, and analysing the characteristic to determine the dominant output wavelength.
    Type: Application
    Filed: February 9, 2009
    Publication date: December 9, 2010
    Applicant: NXP B.V.
    Inventors: Radu Surdeanu, Viet Nguyen Hoang, Benoit Bataillou, Pascal Bancken, David Van Steenwinckel
  • Patent number: 7709387
    Abstract: The method of manufacturing an integrated circuit (IC) according to the invention starts with providing a pre-fabricated integrated circuit (10) comprising an electrical device (2) and having a surface (11) coated with a dielectric material (12) and a metal (15). The dielectric material (12), which may be separated from the metal (15) by the barrier layer (14), has an opening (13), which is filled with the metal (15). Portions of the metal (15) outside the opening (13) are removed by polishing for a first period of time, after which an etching agent (25) is added to the polishing liquid (24) and polishing is continued for a second period of time for removing portions of the metal (15) remaining outside the opening (13). The polishing apparatus (40) is able to perform the method.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: May 4, 2010
    Assignee: NXP B.V.
    Inventors: Viet Nguyen Hoang, Roel Daamen
  • Publication number: 20100090302
    Abstract: A method of making a resonator, preferably a nano-resonator, includes starting with a FINFET structure with a central bar, first and second electrodes connected to the central bar, and third and fourth electrodes on either side of the central bar and separated from the central bar by gate dielectric. The structure is formed on a buried oxide layer. The gate dielectric and buried oxide layer are then selectively etched away to provide a nano-resonator structure with a resonator element 30, a pair of resonator electrodes (32,34), a control electrode (36) and a sensing electrode (38).
    Type: Application
    Filed: October 5, 2007
    Publication date: April 15, 2010
    Applicant: NXP, B.V.
    Inventors: Viet Nguyen Hoang, Dirk Gravesteijn, Radu Surdeanu