Patents by Inventor Viet Nguyen Hoang

Viet Nguyen Hoang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100059894
    Abstract: The invention relates to a method of manufacturing openings in a substrate (5), the method comprising steps of: providing the substrate (5) with a masking layer (40) on a surface thereof; forming a first opening (10), a second opening (30), and a channel (20) in between the first opening (10) and the second opening (30) in the masking layer (40), the channel (20) connecting the first opening (10) with the second opening (30), the second opening (30) having an area (A2) that is larger than the area (A1) of the first opening (10); forming trenches (11, 21, 31) in the substrate (5) located at the first opening (10), the second opening (30), and at the channel (20) under masking of the masking layer (40) by means of anisotropic dry etching, and sealing off the trench (21) located at the channel (20) for forming the openings in the substrate (5). The method of the invention enables formation of a deeper first opening (10) than what is possible with the known methods.
    Type: Application
    Filed: December 10, 2007
    Publication date: March 11, 2010
    Applicant: NXP, B.V.
    Inventors: Viet Nguyen Hoang, Martinus T. Bennebroek
  • Publication number: 20100052180
    Abstract: The invention relates to a semiconductor device manufactured in a process technology, the semiconductor device having at least one wire (135) located in an interconnect layer of said semiconductor device, the at least one wire (135) having a wire width (W) and a wire thickness (T), the wire width (W) being equal to a minimum feature size of the interconnect layer as defined by said process technology, wherein the minimum feature size is smaller than or equal to 0.32 ?m, wherein the aspect ratio (AR) of the at least one wire (135?) is smaller than 1.5, the aspect ratio (AR) being defined as the wire thickness (T) divided by the wire width (W). The invention further discloses a method of manufacturing such a semiconductor device.
    Type: Application
    Filed: June 15, 2007
    Publication date: March 4, 2010
    Applicant: NXP B.V.
    Inventors: Viet Nguyen Hoang, Phillip Christie, Julien M.M. Michelon
  • Publication number: 20090267234
    Abstract: The invention relates to a semiconductor device comprising a substrate (1) and at least one interconnect layer located at a surface of the substrate (1), the interconnect layer comprising a first wire (20?) and a second wire (20?) which are located in the interconnect layer, the first wire (20?) having a first thickness (T1) and the second wire (20?having a second thickness (T2) that is different from the first thickness, the thickness (T1,T2) being defined in a direction perpendicular to said surface. The invention further relates to a method of manufacturing a semiconductor device comprising a substrate (1) and an interconnect layer located at a surface of the substrate (1), the interconnect layer comprising a first wire (20?) and a second wire (20) which are located in the interconnect layer.
    Type: Application
    Filed: June 15, 2007
    Publication date: October 29, 2009
    Applicant: NXP B.V.
    Inventor: Viet Nguyen Hoang
  • Patent number: 7510959
    Abstract: A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises the steps of depositing and patterning a disposable layer, depositing a first barrier layer on top of the patterned disposable layer, depositing a metal layer, planarizing the metal layer, depositing a second barrier layer, planarizing the second barrier layer until substantially no barrier layer material is present on top of the disposable layer, depositing a permeable layer, removing the disposable layer through the permeable layer to form air gaps.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: March 31, 2009
    Assignees: Interuniversitair Microelektronica Centrum (IMEC), Koninklikje Phillips Electronics
    Inventors: Roel Daamen, Viet Nguyen Hoang
  • Patent number: 7491639
    Abstract: The invention relates to the manufacture of a semiconductor device (10) with a semiconductor body (1) and a substrate (2) and comprising at least one semiconductor element (3), which semiconductor device is equipped with at least one connection region (4) and a superjacent strip-shaped connection conductor (5) which is connected to the connection region, which connection region and connection conductor are both recessed in a dielectric, and a dielectric region (6) of a first material is provided on the semiconductor body (1) at the location of the connection region (4) to be formed, after which the dielectric region (6) is coated with a dielectric layer (7) of a second material that differs from the first material, which dielectric layer is provided, at the location of the strip-shaped connection conductor (5) to be formed, with a strip-shaped recess (7A) which overlaps the dielectric region (6) and extends up to said dielectric region, and after the formation of the recess (7A) and the removal of the dielect
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: February 17, 2009
    Assignee: NXP, B.V.
    Inventors: Viet Nguyen Hoang, Dirk Jan Gravesteijn, Romano Julma Oscar Maria Hoofman
  • Publication number: 20060128089
    Abstract: The invention relates to the manufacture of a semiconductor device (10) with a semiconductor body (1) and a substrate (2) and comprising at least one semiconductor element (3), which semiconductor device is equipped with at least one connection region (4) and a superjacent strip-shaped connection conductor (5) which is connected to the connection region, which connection region and connection conductor are both recessed in a dielectric, and a dielectric region (6) of a first material is provided on the semiconductor body (1) at the location of the connection region (4) to be formed, after which the dielectric region (6) is coated with a dielectric layer (7) of a second material that differs from the first material, which dielectric layer is provided, at the location of the strip-shaped connection conductor (5) to be formed, with a strip-shaped recess (7A) which overlaps the dielectric region (6) and extends up to said dielectric region, and after the formation of the recess (7A) and the removal of the dielect
    Type: Application
    Filed: December 15, 2003
    Publication date: June 15, 2006
    Applicant: Koninklijke Philips Electronics N.V.
    Inventors: Viet Nguyen Hoang, Dirk Gravesteijn, Romano Julma Hoofman
  • Patent number: 7025662
    Abstract: The invention relates to an arrangement of a chemical-mechanical polishing tool for chemical-mechanical polishing a surface on a wafer, comprising a polishing pad (4), a drive unit (9), pressing means (6), a wafer holder (5), first dispensing means (7) and second dispensing means (8); the wafer holder for holding a wafer (W) being arranged at a holder location (L0); the pressing means (6) being arranged to press the wafer holder (5) to the polishing pad (4); the first dispensing means (7) for dispensing a first fluid on the polishing pad (4) being arranged at a first dispensing means location (L1); the second dispensing means (8) for dispensing a second fluid on the polishing pad (4) being arranged at a second dispensing means location (L2); the polishing pad (4) comprising a polishing surface for polishing the wafer (W), and the polishing pad (4) further being connected to the drive unit (9) for moving the polishing surface in a first direction (?1) relative to the holder location (L0); wherein the first dis
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: April 11, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Viet Nguyen Hoang, Albert Jan Hof, Herma Van Kranenburg, Pierre Hermanus Woerlee
  • Publication number: 20060014479
    Abstract: The invention relates to an arrangement of a chemical-mechanical polishing tool for chemical-mechanical polishing a surface on a wafer, comprising a polishing pad (4), a drive unit (9), pressing means (6), a wafer holder (5), first dispensing means (7) and second dispensing means (8); the wafer holder for holding a wafer (W) being arranged at a holder location (L0); the pressing means (6) being arranged to press the wafer holder (5) to the polishing pad (4); the first dispensing means (7) for dispensing a first fluid on the polishing pad (4) being arranged at a first dispensing means location (L1); the second dispensing means (8) for dispensing a second fluid on the polishing pad (4) being arranged at a second dispensing means location (L2); the polishing pad (4) comprising a polishing surface for polishing the wafer (W), and the polishing pad (4) further being connected to the drive unit (9) for moving the polishing surface in a first direction (?1) relative to the holder location (L0); wherein the first di
    Type: Application
    Filed: August 3, 2005
    Publication date: January 19, 2006
    Inventors: Viet Nguyen Hoang, Albert Hof, Herma Van Kranenburg, Pierre Woerlee