Patents by Inventor Viet Thanh Dinh

Viet Thanh Dinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250157872
    Abstract: One example discloses a finFet semiconductor device and corresponding manufacturing method is disclosed, the device comprising: a substrate having therein a body-region, a plurality of elongate fins at a first major surface and within the body-region; an oxide layer on the first major surface and partially surrounding a lower portion of the elongate fins; a gate contact extending across and partially surrounding an upper portion of the plurality of elongate fins; a dielectric material, between the fins and the gate region; a plurality of elongate partial fins, parallel thereto and having a height which is less than a height thereof; an elongate metal contact, extending into the substrate and in electrical contact with the partial fins, and forming a body-contact; wherein the elongate metal contact extends between the two of the elongate partial fins and below an upper surface thereof and fills a space therebetween.
    Type: Application
    Filed: November 10, 2023
    Publication date: May 15, 2025
    Inventors: Viet Thanh Dinh, Asanga H. Perera, Sai-Wang Tam
  • Publication number: 20240380365
    Abstract: Embodiments of self-heating tracking circuits for a power amplifier (PA) are disclosed. In an embodiment, a self-heating tracking circuit for a PA includes a PA replica circuit in proximity to the PA and an estimation unit configured to estimate a self-heating time constant of the PA in response to turning on the PA replica circuit and turning off the PA replica circuit.
    Type: Application
    Filed: May 8, 2023
    Publication date: November 14, 2024
    Inventors: Sai-Wang Tam, Viet Thanh Dinh, Juan Xie, Alden C. Wong, Tian Liu, Sri Harsha Kondapalli, Sa-Wey Wu, Ovidiu Carnu
  • Patent number: 11901414
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor region of a first semiconductor type, formed within the semiconductor substrate, wherein the first semiconductor region includes a first doped region formed in a lower portion of the first semiconductor region and a second doped region formed over the first doped region in an upper portion of the first semiconductor region. A defect layer having an upper surface formed in an upper portion of the first doped region. A second semiconductor region of a second semiconductor type is formed over the first semiconductor region.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: February 13, 2024
    Assignee: NXP B.V.
    Inventors: Ljubo Radic, Viet Thanh Dinh, Petrus Hubertus Cornelis Magnee
  • Publication number: 20240014324
    Abstract: A semiconductor device and methods of forming the same include a semiconductive fin protruding vertically from a body region and extending along a first direction, an insulator material above the body region and surrounding a lower portion of the fin, and a gap region between first and second ends of the semiconductive fin where at least a top portion of the semiconductive fin is absent. The device includes current terminals coupled to first and second ends of the fin, and a gate electrode and a gate extension coupled to the fin. The gate electrode surrounds the top portion of the semiconductive fin and is separated from the semiconductive by a gate insulator material. The gate extension has a first end adjacent to the gate electrode and a second end above the body region within the gap region.
    Type: Application
    Filed: July 6, 2022
    Publication date: January 11, 2024
    Inventors: Viet Thanh Dinh, Asanga H. Perera, Arjan Mels
  • Publication number: 20230081675
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor region of a first semiconductor type, formed within the semiconductor substrate, wherein the first semiconductor region includes a first doped region formed in a lower portion of the first semiconductor region and a second doped region formed over the first doped region in an upper portion of the first semiconductor region. A defect layer having an upper surface formed in an upper portion of the first doped region. A second semiconductor region of a second semiconductor type is formed over the first semiconductor region.
    Type: Application
    Filed: September 7, 2021
    Publication date: March 16, 2023
    Inventors: Ljubo Radic, Viet Thanh Dinh, Petrus Hubertus Cornelis Magnee
  • Patent number: 11532546
    Abstract: A fringe capacitor comprises a plurality of unidirectional metal layers, wherein an orientation of a preferred direction of each of the unidirectional metal layers is in a same direction. First fingers of the fringe capacitor are formed in a first layer of the unidirectional metal layers, the first fingers being interdigitated and having a direction parallel to the orientation of the preferred direction. Second fingers of the fringe capacitor are formed in a second layer of the unidirectional metal layers, the second fingers being interdigitated and having a direction parallel to the orientation of the preferred direction, the first layer and the second layer separated by at least a layer of not having the orientation of the preferred direction and not having fingers of the fringe capacitor.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: December 20, 2022
    Assignee: NXP B.V.
    Inventors: Viet Thanh Dinh, Bartholomeus Wilhelmus Christiaan Hovens, Marina Vroubel
  • Publication number: 20220344257
    Abstract: A fringe capacitor comprises a plurality of unidirectional metal layers, wherein an orientation of a preferred direction of each of the unidirectional metal layers is in a same direction. First fingers of the fringe capacitor are formed in a first layer of the unidirectional metal layers, the first fingers being interdigitated and having a direction parallel to the orientation of the preferred direction.
    Type: Application
    Filed: April 26, 2021
    Publication date: October 27, 2022
    Inventors: Viet Thanh Dinh, Bartholomeus Wilhelmus Christiaan Hovens, Marina Vroubel
  • Patent number: 10580906
    Abstract: A semiconductor device comprising a pn junction diode and a method of making the same. The device includes a semiconductor substrate having a first conductivity type. The device also includes a buried oxide layer located in the substrate. The device further includes a semiconductor region having a second conductivity type extending beneath the buried oxide layer to form a pn junction with a semiconductor region having the first conductivity type. The pn junction is located beneath the buried oxide layer and extends substantially orthogonally with respect to a major surface of the substrate. The device also includes a field plate electrode comprising a semiconductor region located above the buried oxide layer for modifying an electric field at the pn junction by application of a potential to the field plate electrode.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: March 3, 2020
    Assignee: NXP B.V.
    Inventors: Viet Thanh Dinh, Marina Vroubel, Paul Alexander Grudowski
  • Patent number: 10381447
    Abstract: A Field Effect Transistor (FET) capable of operating at high frequencies and includes comb-shaped source and drain electrodes. The comb-shaped drain electrode includes a plurality of thin comb-shape drain electrode layers at corresponding levels of the FET, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped drain electrodes of each other layer. The comb-shaped source electrode includes a plurality of comb-shape source electrode layers at the corresponding levels, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped source electrodes of each other layer. In addition, the inter-level retraction of adjacent drain electrode layers is the same or substantially the same. Similarly, the inter-level retraction of adjacent source electrode layers is the same or substantially the same.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 13, 2019
    Assignee: NXP B.V.
    Inventors: Lukas Frederik Tiemeijer, Viet Thanh Dinh, Valerie Marthe Girault
  • Publication number: 20190181234
    Abstract: A Field Effect Transistor (FET) capable of operating at high frequencies and includes comb-shaped source and drain electrodes. The comb-shaped drain electrode includes a plurality of thin comb-shape drain electrode layers at corresponding levels of the FET, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped drain electrodes of each other layer. The comb-shaped source electrode includes a plurality of comb-shape source electrode layers at the corresponding levels, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped source electrodes of each other layer. In addition, the inter-level retraction of adjacent drain electrode layers is the same or substantially the same. Similarly, the inter-level retraction of adjacent source electrode layers is the same or substantially the same.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 13, 2019
    Inventors: Lukas Frederik Tiemeijer, Viet Thanh Dinh, Valerie Marthe Girault
  • Patent number: 10250258
    Abstract: Embodiments of devices and method for detecting semiconductor substrate thickness are disclosed. In an embodiment, an IC device includes a semiconductor substrate, a charge emitter embedded in the semiconductor substrate and configured to produce an electrical charge in the semiconductor substrate and a charge sensor embedded in the semiconductor substrate and configured to generate a response signal in response to the electrical charge produced in the semiconductor substrate. The magnitude of the response signal depends on the thickness of the semiconductor substrate.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: April 2, 2019
    Assignee: NXP B.V.
    Inventors: Andreas Bernardus Maria Jansman, Franciscus Petrus Widdershoven, Viet Thanh Dinh
  • Patent number: 10134860
    Abstract: A semiconductor device includes a first dielectric layer on a substrate, the first dielectric layer including a first dielectric portion over a first doped well region of a first conductivity type and a second dielectric portion over a second doped well region of a second conductivity type, and a second dielectric layer on the substrate directly adjacent the first dielectric layer. The second dielectric layer is over the second doped well region. A first conductive gate structure is over the first and second dielectric layers. A third dielectric layer is on the substrate over the second doped well region and separated a first distance from the second dielectric layer. A second conductive gate structure is over the third dielectric layer. A third doped region of the second conductivity type is implanted in the second doped well region a second distance from the third dielectric layer and the second conductive gate structure.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: November 20, 2018
    Assignee: NXP B.V.
    Inventors: Jan Sonsky, Viet Thanh Dinh, Jan Claes
  • Publication number: 20180261676
    Abstract: A semiconductor device includes a first dielectric layer on a substrate, the first dielectric layer including a first dielectric portion over a first doped well region of a first conductivity type and a second dielectric portion over a second doped well region of a second conductivity type, and a second dielectric layer on the substrate directly adjacent the first dielectric layer. The second dielectric layer is over the second doped well region. A first conductive gate structure is over the first and second dielectric layers. A third dielectric layer is on the substrate over the second doped well region and separated a first distance from the second dielectric layer. A second conductive gate structure is over the third dielectric layer. A third doped region of the second conductivity type is implanted in the second doped well region a second distance from the third dielectric layer and the second conductive gate structure.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 13, 2018
    Inventors: JAN SONSKY, VIET THANH DINH, JAN CLAES
  • Patent number: 10043894
    Abstract: Disclosed is a transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: August 7, 2018
    Assignee: NXP B.V.
    Inventors: Viet Thanh Dinh, Tony Vanhoucke, Evelyne Gridelet, Anco Heringa, Jan Willem Slotboom, Dirk Klaassen
  • Patent number: 10014398
    Abstract: The disclosure relates to bipolar transistor devices and a method of fabricating the same. The device comprises a field plate, in an isolation region adjacent to a base-collector junction of said active region. The isolation region comprises a gate terminal arranged to be biased independently of a collector, base or emitter terminal of said transistor.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: July 3, 2018
    Assignee: NXP B.V.
    Inventors: Johannes Donkers, Viet Thanh Dinh, Tony Vanhoucke, Evelyne Gridelet, Anco Heringa, Dirk Klaassen
  • Publication number: 20180091147
    Abstract: Embodiments of devices and method for detecting semiconductor substrate thickness are disclosed. In an embodiment, an IC device includes a semiconductor substrate, a charge emitter embedded in the semiconductor substrate and configured to produce an electrical charge in the semiconductor substrate and a charge sensor embedded in the semiconductor substrate and configured to generate a response signal in response to the electrical charge produced in the semiconductor substrate. The magnitude of the response signal depends on the thickness of the semiconductor substrate.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Applicant: NXP B.V.
    Inventors: Andreas Bernardus Maria Jansman, Franciscus Petrus Widdershoven, Viet Thanh Dinh
  • Patent number: 9905679
    Abstract: A semiconductor device comprising a bipolar transistor and a method of making the same. The bipolar transistor includes a collector having a laterally extending drift region. The bipolar transistor also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a reduced surface field (RESURF) gate located above an upper surface of the laterally extending drift region for shaping an electric field within the collector. The bipolar transistor further includes a gap located between the reduced surface field gate and an extrinsic region of the base of the device, for electrically isolating the reduced surface field gate from the base. A lateral dimension Lgap of the gap is in the range 0.1 ?m?Lgap?1.0 ?m.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: February 27, 2018
    Assignee: NXP B.V.
    Inventors: Petrus Hubertus Cornelis Magnee, Joost Melai, Viet Thanh Dinh, Tony Vanhoucke
  • Publication number: 20170229564
    Abstract: The disclosure relates to bipolar transistor devices and a method of fabricating the same. The device comprises a field plate, in an isolation region adjacent to a base-collector junction of said active region. The isolation region comprises a gate terminal arranged to be biased independently of a collector, base or emitter terminal of said transistor.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Inventors: Johannes Donkers, Viet Thanh Dinh, Tony Vanhoucke, Evelyne Gridelet, Anco Heringa, Dirk Klaassen
  • Patent number: 9570546
    Abstract: A semiconductor device comprising a bipolar transistor and a method of making the same. A power amplifier including a bipolar transistor. The bipolar transistor includes a collector including a laterally extending drift region. The also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a doped region having a conductivity type that is different to that of the collector. The doped region extends laterally beneath the collector to form a junction at a region of contact between the doped region and the collector. The doped region has a non-uniform lateral doping profile. A doping level of the doped region is highest in a part of the doped region closest to a collector-base junction of the bipolar transistor.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: February 14, 2017
    Assignee: NXP B.V.
    Inventors: Tony Vanhoucke, Viet Thanh Dinh, Petrus Hubertus Cornelis Magnee, Ponky Ivo, Dirk Klaassen, Mahmoud Shehab Mohammad Al-Sa'di
  • Patent number: 9515644
    Abstract: A circuit, comprising a semiconductor device with one or more field gate terminals for controlling the electric field in a drift region of the semiconductor device; and a feedback circuit configured to dynamically control a bias voltage or voltages applied to the field gate terminal or terminals, with different control voltages used for different semiconductor device characteristics in real-time in response to a time-varying signal at a further node in the circuit.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: December 6, 2016
    Assignee: NXP B.V.
    Inventors: Viet Thanh Dinh, Godefridus Antonius Maria Hurxk, Tony Vanhoucke, Jan Willem Slotboom, Anco Heringa, Ivan Zahariev, Evelyne Gridelet