Patents by Inventor Vignesh SUNDAR

Vignesh SUNDAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11956971
    Abstract: A fabrication process for an STT MTJ MRAM device includes steps of cooling the device at individual or at multiple stages in its fabrication. The cooling process, which may be equally well applied during the fabrication of other multi-layered devices, is demonstrated to produce an operational device that is more resistant to adverse thermal effects during operation that would normally cause a similar device not so fabricated to lose stored data and otherwise fail to operate properly.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huanlong Liu, Guenole Jan, Ru-Ying Tong, Jian Zhu, Yuan-Jen Lee, Jodi Mari Iwata, Sahil Patel, Vignesh Sundar
  • Patent number: 11903324
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Wang, Dongna Shen, Vignesh Sundar, Sahil Patel
  • Patent number: 11849646
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, a capping layer that is a conductive metal nitride such as MoN contacts an opposite surface of the Hk enhancing layer with respect to the first interface to reduce interdiffusion of oxygen and nitrogen compared with a TiN capping layer and maintain an acceptable resistance×area (RA) product. In other embodiments, the capping layer may comprise an insulating nitride such as AlN that is alloyed with a conductive metal to minimize RA. Furthermore, a metallic buffer layer may be inserted between the capping layer and Hk enhancing layer. As a result, electrical shorts are reduced and the magnetoresistive ratio is increased.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong, Vignesh Sundar, Jian Zhu, Huanlong Liu
  • Publication number: 20230389435
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Yi Yang, Dongna Shen, Vignesh Sundar, Yu-Jen Wang
  • Publication number: 20230371398
    Abstract: A magnetic tunneling junction (MTJ) structure is described. The MJT structure includes a stress modulating layer on a first electrode layer, where a material of the stress modulating layer is different from a material of the first electrode layer. The MJT structure further includes a MTJ material stack on the stress modulating layer. And the MJT structure further includes a second electrode layer on the MTJ material stack. The stress modulating layer reduces crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Jesmin Haq, Tom Zhong, Vinh Lam, Vignesh Sundar, Zhongjian Teng
  • Patent number: 11818961
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Vignesh Sundar, Yu-Jen Wang
  • Patent number: 11785864
    Abstract: A magnetic tunneling junction (MTJ) structure is described. The MJT structure includes a stress modulating layer on a first electrode layer, where a material of the stress modulating layer is different from a material of the first electrode layer. The MJT structure further includes a MTJ material stack on the stress modulating layer. And the MJT structure further includes a second electrode layer on the MTJ material stack. The stress modulating layer reduces crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Jesmin Haq, Tom Zhong, Vinh Lam, Vignesh Sundar, Zhongjian Teng
  • Publication number: 20230217834
    Abstract: A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.
    Type: Application
    Filed: March 10, 2023
    Publication date: July 6, 2023
    Inventors: Vignesh Sundar, Yi Yang, Dongna Shen, Zhongjian Teng, Jesmin Haq, Sahil Patel, Yu-Jen Wang, Tom Zhong
  • Patent number: 11696511
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H2, or a reducing species.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sahil Patel, Guenole Jan, Ru-Ying Tong, Vignesh Sundar, Dongna Shen, Yu-Jen Wang, Po-Kang Wang, Huanlong Liu
  • Patent number: 11631802
    Abstract: A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: April 18, 2023
    Assignee: Headway Technologies, Inc.
    Inventors: Vignesh Sundar, Yi Yang, Dongna Shen, Zhongjian Teng, Jesmin Haq, Sahil Patel, Yu-Jen Wang, Tom Zhong
  • Publication number: 20230060687
    Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2 configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance×area (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable magnetoresistive ratio (DRR). Moreover, first and second pinned layers, PL1 and PL2, respectively, have magnetizations that are aligned antiparallel to enable a lower critical switching current that when in a parallel alignment. The condition RA1<RA2 is achieved with one or more of a smaller thickness and a lower oxidation state for TB1 compared with TB2, with conductive (metal) pathways formed in a metal oxide or metal oxynitride matrix for TB1, or with a TB1 containing a dopant to create conducting states in the TB1 band gap. Alternatively, TB1 may be replaced with a metallic spacer to improve conductivity between PL1 and the FL.
    Type: Application
    Filed: November 7, 2022
    Publication date: March 2, 2023
    Inventors: Vignesh Sundar, Yu-Jen Wang, Luc Thomas, Guenole Jan
  • Publication number: 20220384718
    Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.
    Type: Application
    Filed: July 27, 2022
    Publication date: December 1, 2022
    Inventors: Vignesh Sundar, Yu-Jen Wang, Dongna Shen, Sahil Patel, Ru-Ying Tong
  • Publication number: 20220384713
    Abstract: A magnetic tunneling junction (MTJ) structure is described. The MJT structure includes a stress modulating layer on a first electrode layer, where a material of the stress modulating layer is different from a material of the first electrode layer. The MJT structure further includes a MTJ material stack on the stress modulating layer. And the MJT structure further includes a second electrode layer on the MTJ material stack. The stress modulating layer reduces crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Inventors: Jesmin Haq, Tom Zhong, Vinh Lam, Vignesh Sundar, Zhongjian Teng
  • Publication number: 20220384716
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, a capping layer that is a conductive metal nitride such as MoN contacts an opposite surface of the Hk enhancing layer with respect to the first interface to reduce interdiffusion of oxygen and nitrogen compared with a TiN capping layer and maintain an acceptable resistance x area (RA) product. In other embodiments, the capping layer may comprise an insulating nitride such as AlN that is alloyed with a conductive metal to minimize RA. Furthermore, a metallic buffer layer may be inserted between the capping layer and Hk enhancing layer. As a result, electrical shorts are reduced and the magnetoresistive ratio is increased.
    Type: Application
    Filed: July 26, 2022
    Publication date: December 1, 2022
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong, Vignesh Sundar, Jian Zhu, Huanlong Liu
  • Publication number: 20220367793
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: Yi YANG, Dongna SHEN, Vignesh SUNDAR, Yu-Jen WANG
  • Publication number: 20220359821
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Yu-Jen Wang, Dongna Shen, Vignesh Sundar, Sahil Patel
  • Patent number: 11495738
    Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2 configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance×area (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable magnetoresistive ratio (DRR). Moreover, first and second pinned layers, PL1 and PL2, respectively, have magnetizations that are aligned antiparallel to enable a lower critical switching current that when in a parallel alignment. The condition RA1<RA2 is achieved with one or more of a smaller thickness and a lower oxidation state for TB1 compared with TB2, with conductive (metal) pathways formed in a metal oxide or metal oxynitride matrix for TB1, or with a TB1 containing a dopant to create conducting states in the TB1 band gap. Alternatively, TB1 may be replaced with a metallic spacer to improve conductivity between PL1 and the FL.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Vignesh Sundar, Yu-Jen Wang, Luc Thomas, Guenole Jan
  • Patent number: 11444241
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Vignesh Sundar, Yu-Jen Wang
  • Patent number: 11430945
    Abstract: A method for fabricating an improved magnetic tunneling junction (MTJ) structure is described. A bottom electrode is provided on a substrate. A MTJ stack is deposited on the bottom electrode. A top electrode is deposited on the MTJ stack. A first stress modulating layer is deposited between the bottom electrode and the MTJ stack, or a second stress modulating layer is deposited between the MTJ stack and the top electrode, or both a first stress modulating layer is deposited between the bottom electrode and the MTJ stack and a second stress modulating layer is deposited between the MTJ stack and the top electrode. The top electrode and MTJ stack are patterned and etched to form a MTJ device. The stress modulating layers reduce crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jesmin Haq, Tom Zhong, Vinh Lam, Vignesh Sundar, Zhongjian Teng
  • Patent number: 11424405
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Wang, Dongna Shen, Vignesh Sundar, Sahil Patel