Patents by Inventor Vijay Anand

Vijay Anand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12282732
    Abstract: A method of automated review of communications comprises: receiving, by a computer system, a document from a requestor application; extracting layout information and text from the document; extracting, based on the layout information, values of one or more predefined data items from the text of the document; producing a document validation result by analyzing the one or more data items; embedding, into the document, one or more human-readable comments reflecting the document validation result; and forwarding, to the requestor application, the document comprising the one or more human readable comments.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: April 22, 2025
    Assignee: Nuveen Investments, Inc.
    Inventors: Johanna Anders, John Rybczynski, Sai Vijay Anand Ponduru, Vinay Abhishek Akkana, Sivakumar Muthusamy, Santanu Sengupta
  • Patent number: 12279152
    Abstract: Systems, methods, and circuitries are provided for using an application Layer 2 buffer for reordering out of sequence (OOS) packets when possible to reduce an amount of memory allocated to a baseband (BB) Layer 2 (L2) buffer. In one example, a baseband circuitry of a user equipment (UE), includes BB memory, configured as a BB L2 buffer and one or more BB processors. The BB processors are configured to receive an OOS packet from a physical layer; and in response to an APP L2 buffer status indicating at least a first amount of memory is available, send the OOS packet to APP circuitry for storing in an APP L2 buffer.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: April 15, 2025
    Assignee: Apple Inc.
    Inventors: Abhishek Anand Konda, Bobby Jose, Vijay Venkataraman
  • Patent number: 12248348
    Abstract: The present invention provides a system and method for optimizing BOM cost of platform SoC for Battery management system. The system (100) comprises a sensor (101), coupled with the device to receive input physical parameters Temperature, Voltage and current and a CPU with SIMD extensions without saturation logic in the instruction set and floating-point unit, wherein Battery management module is implemented (101). Using CPU with SIMD extensions instead of DSPNLIW core in platform SoC helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results overcoming the limitations of CPU ISA as against DSP ISA. The power consumed in either case (Battery management implementation on CPU, DSP ISA) is the same, thus giving value additions to platform SoC designers and makers.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: March 11, 2025
    Assignee: TriSpace Technologies (OPC) Pvt. Ltd.
    Inventors: Narasimhan Vijay Anand, Indhushree Devaraja, Krishnakumar Gopinath, Gangadhar Kamarthi Guruswamy
  • Publication number: 20250080477
    Abstract: Techniques in dynamic routing for advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element comprises a compute element enabled to execute programmed instructions using the data and a router enabled to route the wavelets via static routing, dynamic routing, or both. The routing is in accordance with a respective virtual channel specifier of each of the wavelets and controlled by routing configuration information of the router. The static techniques enable statically specifiable neuron connections. The dynamic techniques enable information from the wavelets to alter the routing configuration information during neural network processing.
    Type: Application
    Filed: November 12, 2024
    Publication date: March 6, 2025
    Inventors: Michael Morrison, Michael Edwin James, Sean Lie, Srikanth Arekapudi, Gary R. Lauterbach, Vijay Anand Reddy KORTHIKANTI
  • Patent number: 12229019
    Abstract: Embodiments are described for a method and system of applying data protection software mechanisms to network devices to auto-discover the networking equipment, save changes from memory (TCAM) to local storage, backup changes to protection storage, provide auditing and tracking history of changes, and provide the ability to deploy test/development copies of changes using software defined networking techniques. Embodiments include an efficient visual mapping aspect provided through a GUI to display the topography and backup/protection configuration of network devices in a system.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: February 18, 2025
    Assignee: EMC IP Holding Company LLC
    Inventors: Arun Murti, Adam Brenner, Mark Malamut, Vijay Anand
  • Publication number: 20250030907
    Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for modifying one or more parameters of a data streaming bitrate selection algorithm based on machine learning. An example embodiment operates by training and operating a first machine learning model to predict a sustainable network bandwidth. A second machine learning model is trained to receive the sustainable network bandwidth and predict a likelihood that this network bandwidth will not empty a data buffer of streaming data. A bitrate is selected based on the likelihood being below a threshold percentage, such as 50%.
    Type: Application
    Filed: October 4, 2024
    Publication date: January 23, 2025
    Applicant: ROKU, INC.
    Inventors: Amit PALIWAL, Andrey MARSAVIN, Govind VAIDYA, Wim MICHIELS, Beth Teresa LOGAN, Zheng HAN, Tapan OZA, Vijay Anand RAGHAVAN
  • Publication number: 20250014306
    Abstract: The present invention provides a system and method for detection and identification of feature sub-image in a given image. The system (100) comprises single CPY core with Single Instruction Multiple Data (SIMD) instruction set but the instructions lack saturation logic (101), wherein the software modules are implemented. Removing the logic hardware used to implement saturation in the SIMD instructions helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results without saturation logic. The power consumed using CPU without saturation logic in SIMD instruction is lesser than using Digital Signal Processing Instruction Set Architecture with saturation logic, thus giving value additions to platform SoC designers and makers for using low BoM cost solution.
    Type: Application
    Filed: July 26, 2023
    Publication date: January 9, 2025
    Inventors: Narasimhan Vijay Anand, Thirumuru Chakradhar Reddy
  • Publication number: 20250016322
    Abstract: The present invention provides a system and method for optimizing BoM cost and power performance drones. The system (100) comprises dual CPU cores with Single Instruction Multiple Data (SIMD) instruction set but the instructions lack saturation logic (101), wherein control software modules is implemented. Video codec encoder modules (102) are implemented in the second CPU with SIMD instruction set lacking saturation logic. Removing the logic hardware used to implement saturation in the SIMD instructions helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results without saturation logic. The power consumed using CPU without saturation logic in SIMD instruction is lesser than using Digital Signal Processing Instruction Set Architecture with saturation logic, thus giving value additions to platform SoC designers and makers for using low BoM cost solution with better power performance.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 9, 2025
    Inventors: Narasimhan Vijay Anand, Chandana M S, Kamarsu Venkata Sriya, Mohammed Amrin Bushra Taj, Akshay Madavalappil Ramesh, Lellapalli Anagha
  • Publication number: 20250014308
    Abstract: The present invention provides a system and method for extracting Tropological features from an image. The system (100) comprises CPU core with Single Instruction Multiple Data (SIMD) instruction set but the instructions lack saturation logic (101), wherein the software modules are implemented. Removing the logic hardware used to implement saturation in the SIMD instructions helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results without saturation logic. The power consumed using CPU without saturation logic in SIMD instruction is lesser than using Digital Signal Processing Instruction Set Architecture with saturation logic, thus giving value additions to platform SoC designers and makers for using low BoM cost solution.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 9, 2025
    Inventors: Narasimhan Vijay Anand, Yashna Karkera
  • Publication number: 20250008133
    Abstract: The present invention provides a system and method for optimizing BOM cost of Graphics Processing Unit GPU core. The system (100) comprises a GPU with typical compute unit and instruction set of a GPU but the video SIMD instructions lacking saturation logic (101), wherein Video codec encoder/decoder modules is implemented. In-loop Deblocking filter, post-processing filtering module (102) are implemented in the GPU. Removing the logic hardware used to implement saturation in the video SIMD instructions helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results without saturation logic. The power consumed without saturation logic is lesser than one in with saturation logic is used, thus giving value additions to platform SoC designers and makers for using lo BoM cost GPU with better power performance.
    Type: Application
    Filed: July 24, 2023
    Publication date: January 2, 2025
    Inventors: Narasimhan Vijay Anand, Mohammed Amrin Bushra Taj, Akshay Madavalappil Ramesh, Lellapalli Anagha, Kamarsu Venkata Sriya
  • Publication number: 20250004517
    Abstract: The present invention provides a system and method for optimizing BOM cost of platform SoC for Battery management system. The system (100) comprises a sensor (101), coupled with the device to receive input physical parameters Temperature, Voltage and current and a CPU with SIMD extensions without saturation logic in the instruction set and floating-point unit, wherein Battery management module is implemented (101). Using CPU with SIMD extensions instead of DSPNLIW core in platform SoC helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results overcoming the limitations of CPU ISA as against DSP ISA. The power consumed in either case (Battery management implementation on CPU, DSP ISA) is the same, thus giving value additions to platform SoC designers and makers.
    Type: Application
    Filed: July 24, 2023
    Publication date: January 2, 2025
    Inventors: Narasimhan Vijay Anand, Indhushree Devaraja, Krishnakumar Gopinath, Gangadhar Kamarthi Guruswamy
  • Publication number: 20250008188
    Abstract: Disclosed herein are system, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for performing context classification of streaming content using machine learning (ML). In an embodiment, a streaming media client receives an audio/video (A/V) stream that represents a portion of content to be played back by the client. The client reconstructs a sequence of video frames from the A/V stream, extracts audio information from the A/V stream, and executes an ML based classifier to predict a context label associated with the portion of content based at least on one or more video frames from the sequence of video frames and the audio information. The client then transmits the context label to a streaming media service. The service may use the context label to select an advertisement or content recommendation to send to the client or to select a set of content streaming parameters for the client.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: SAYAN MAITY, JUHI CHECKER, BETH TERESA LOGAN, ERWIN BELLERS, JOHAN JANSSEN, VIJAY ANAND RAGHAVAN, ANDREW LARDIERE, WEIMING ZHANG
  • Patent number: 12177133
    Abstract: Techniques in dynamic routing for advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element comprises a compute element enabled to execute programmed instructions using the data and a router enabled to route the wavelets via static routing, dynamic routing, or both. The routing is in accordance with a respective virtual channel specifier of each of the wavelets and controlled by routing configuration information of the router. The static techniques enable statically specifiable neuron connections. The dynamic techniques enable information from the wavelets to alter the routing configuration information during neural network processing.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: December 24, 2024
    Assignee: Cerebras Systems Inc.
    Inventors: Michael Morrison, Michael Edwin James, Sean Lie, Srikanth Arekapudi, Gary R. Lauterbach, Vijay Anand Reddy Korthikanti
  • Patent number: 12137265
    Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for modifying one or more parameters of a data streaming bitrate selection algorithm based on machine learning. An example embodiment operates by training and operating a first machine learning model to predict a sustainable network bandwidth. A second machine learning model is trained to receive the sustainable network bandwidth and predict a likelihood that this network bandwidth will not empty a data buffer of streaming data. A bitrate is selected based on the likelihood being below a threshold percentage, such as 50%.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: November 5, 2024
    Assignee: Roku, Inc.
    Inventors: Amit Paliwal, Andrey Marsavin, Govind Vaidya, Wim Michiels, Beth Teresa Logan, Zheng Han, Tapan Oza, Vijay Anand Raghavan
  • Patent number: 12117469
    Abstract: A scheme for measuring AC and DC load-line (LL) using voltage and current monitoring apparatus. During calibration for LL measurement, a tested or known workload is executed on a processor or system-on-chip (SoC). The calibration can be done when the processor is first used in a real-time system (customer) scenario, or repeated whenever necessary to compensate silicon aging or other effects that affect the LL values. LL is estimated, determined, and/or calculated for each power supply rail in the processor or SoC. The measured LL is used in calculations that determine the operating voltage of an input voltage regulator (VR) at run time, thereby optimizing the power/performance characteristics of that specific system.
    Type: Grant
    Filed: December 19, 2020
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Vijay Anand Mathiyalagan, Stephen Gunther
  • Publication number: 20240211016
    Abstract: A system includes a resource controller that can determine if a memory has been idle for longer than a threshold. The resource controller is at the system level, above the memory subsystem. In response to determining the memory has been idle for at least the threshold, the resource controller can trigger the memory controller to send a shallow self-refresh command, which is self-refresh without clock stop.
    Type: Application
    Filed: March 7, 2024
    Publication date: June 27, 2024
    Inventors: Vijay Anand MATHIYALAGAN, Michelle M. WIGTON
  • Publication number: 20240183884
    Abstract: Embodiments herein relate to a chiplet or other die which includes multiple sense points within the die and components for digitizing and outputting sensed voltages of the sense points. In one approach, an analog-to-digital converter (ADC) is coupled to each sense point, and a multiplexer is coupled to the outputs of the ADCs. A select signal for the multiplexer can be received from an external control unit which selects one of the sense points based on information such as a current workflow of the die. The selected sense point can change as the workflow changes. The optimal sense point can be determined by comparing the voltage of each sense point and selecting the sense point with the lowest voltage. The sensed voltage is provided to a voltage regulator as a feedback signal to optimize control of the power supply of the die.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 6, 2024
    Inventors: Vikrant Thigle, Vijay Anand Mathiyalagan, Anand Haridass, Arun Chandrasekhar, Gerald Pasdast
  • Publication number: 20240111598
    Abstract: In an embodiment, a processor may include a plurality of processing engines and a sequencing circuit. The sequencing circuit may be to: detect a completed execution of a first workload by a first processing engine; in response to a detection of the completed execution of the first workload by the first processing engine, identify at least one processing engine specified as consecutive to the first processing engine in a sequence mapping; and activate the at least one processing engine specified as consecutive to execute a second workload.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Shidlingeshwar Khatakalle, Vijay Anand Mathiyalagan, Diyanesh Babu Chinnakkonda Vidyapoornachary
  • Publication number: 20240112006
    Abstract: A network of matrix processing units (MPUs) is provided on a device, where each MPU is connected to at least one other MPU in the network, and each MPU is to perform matrix multiplication operations. Computer memory stores tensor data and a master control central processing unit (MCC) is provided on the device to receive an instruction from a host device, where the instruction includes one or more tensor operands based on the tensor data. The MCC invokes a set of operations on one or more of the MPUs based on the instruction, where the set of operations includes operations on the tensor operands. A result is generated from the set of operations, the result embodied as a tensor value.
    Type: Application
    Filed: December 8, 2023
    Publication date: April 4, 2024
    Inventors: Horace H. Lau, Prashant Arora, Olivia K. Wu, Tony L. Werner, Carey K. Kloss, Amir Khosrowshahi, Andrew Yang, Aravind Kalaiah, Vijay Anand R. Korthikanti
  • Publication number: 20240096466
    Abstract: A system and method for a protocol to identify patterns among caregivers and predict the root cause of burnout, whereby the system leverages proprietary data and data collected form third party sources to assess the risk of caregivers and then adjusts accordingly based on previous data of the caregivers as well as other similar caregivers.
    Type: Application
    Filed: September 20, 2022
    Publication date: March 21, 2024
    Inventors: Mohammad Ali Ahmadi, Michael Mings, Vijay Anand