Abstract: An embodiment of the present invention provides an apparatus, comprising a multi-band highly isolated planar antenna directly integrated with a front-end module (FEM).

Abstract: An apparatus includes a coreless substrate with an embedded die that is integral to the coreless substrate, and at least one device assembled on a surface that is opposite to a ball-grid array disposed on the coreless substrate. The apparatus may include an over-mold layer to protect the at least one device assembled on the surface.

Abstract: An embodiment of the present invention provides an apparatus, comprising a multi-band highly isolated planar antenna directly integrated with a front-end module (FEM).

Abstract: A wireless device using natural higher order harmonics on multi-band reconfigurable antenna designs where the antenna higher order resonance is used to build a multi-band to multi-band frequency reconfigurable antenna.

Abstract: Efficient cell lysis in small samples, i.e., samples less than one milliliter, is achieved by exposing the sample to microwave radiation in the frequency range of 18 to 26 GHz. The sample containing cells is supported in a wave-guide cavity, and a microwave source provides microwave radiation to the input port of the wave-guide cavity. A computer controls the frequency and source power level of the microwave radiation produced by the microwave source. The computer also monitors the input power level of the microwave radiation at the input port by means of an input power measuring instrument, the output power level at the output port by means of an output power measuring instrument, and the temperature of the sample by means of a thermocouple. In this way, the computer can control the operating parameters to achieve efficient cell lysis.

Abstract: An electrically active antenna apparatus comprising a substrate, a RF feed positioned on the substrate, a radiator element positioned on the substrate and adjacent to the RF feed such that the radiator element and the RF feed are electromagnetically coupled, and a plurality of active devices that make electrical contact with the radiator element. The plurality of active devices are biased to actively tune the resonance frequency of the radiator element.

Abstract: A semiconductor device includes a buffer layer (23) having a doped region (24), a barrier layer (26) over the buffer layer (23) and having a doped region (27), and a channel layer (25) located between the buffer layer (23) and the barrier layer (26) where the doping density of the doped region (27) in the barrier layer (26) is higher than the doping densities of the channel layer (25) and the doped region (24) in the first buffer layer (23).

Abstract: A VCO includes a transistor having a plurality of negative differential resistance devices coupled in series to the source terminal of the transistor, with each of the devices having a negative differential resistance operating region. Biasing circuits are coupled to the drain and gate terminals along with operating voltages which set the oscillator to operating in a negative differential resistance region of at least one of the negative differential resistance devices so that oscillations of a selected frequency are produced at an output terminal. The transistor, the plurality of N devices, the DC biasing circuits, and the operating voltages are connected so that the oscillator negative differential resistance operating region is greater than N times as wide as each of the device negative differential operating regions individually.

Abstract: A high efficiency power amplifier includes an integrated circuit with a heterojunction interband tunneling field effect transistor (HITFET) amplifier coupled to receive high frequency (into the GHz) RF signals. The HITFET amplifier is constructed to receive the RF signal with a given frequency at the input terminal and to produce a substantially square wave signal at the given frequency at an output terminal in response to the RF signal applied to the input terminal. The gate of a switching FET connected as a class E amplifier is coupled to the output of the HITFET for receiving the square wave signal and an impedance matching output circuit is coupled to the drain of the switching FET.

Abstract: A heterostructure field effect transistor and method including at least one passivation layer (20) and at least one etch stop layer (22). Enhancement, depletion and combined devices with both enhancement mode and depletion mode devices are possible with minor process variations. Refractory gate (40) and non-gold refractory ohmic contact (52) metallization combined with other features allows non-liftoff metal patterning.

Abstract: A dual voltage controlled oscillator including a transistor with a negative differential resistance diode coupled to a first terminal and an inductance coupled to a second terminal. Operating voltages are applied to the gate and drain of the transistor to set the oscillator to operating in a negative differential resistance region of the diode. The diode, the inductance and the operating voltages are connected so that varying either of the operating voltages varies the frequency of the oscillations at the output.

Abstract: An amplifier (10) receives a bias voltage to the gate of a depletion mode field effect transistor (12). In one embodiment, a bias circuit (20) offsets (22) the bias voltage from a power supply potential (26) to maintain substantially constant drain current over a range of threshold voltages (34,36,38) caused by process and temperature variation. In an alternate embodiment, a transistor (58) in the bias circuit (50) provides an incremental current flow to compensate the bias voltage of the MESFET for variation in threshold voltages. The bias circuit is applicable to other depletion mode field effect transistor circuits having a negative threshold voltage.

Abstract: A low power heterojunction field effect transistor (10, 30, 50, 60) capable of operating at low drain currents while having a low intermodulation distortion. A channel restriction region (9, 38, 51) is formed between the gate electrodes (24, 41, 69) and the drain electrodes (25, 46, 65). The channel restriction region (9, 38, 51) depletes the channel layer (13, 33) thereby constricting a channel and lowering a drain saturation current. The channel restriction region (9, 38, 51) may be used to set a desired drain saturation current such that a second derivative of the transconductance with respect to the gate-source voltage is approximately zero and a first derivative of the transconductance with respect to the gate-source voltage is, approximately, a relative maximum at the desired operating point.

Abstract: A frequency mixer circuit uses an impedance transforming power combiner to sum the power levels of RF and LO input signals and drive an output field effect transistor (FET). The nonlinear transconductance in the FET creates the sum and difference mixing products for providing an IF output signal operating at a frequency equal to the difference between the frequencies of the RF and LO input signals. The power combiner is impedance matched to the gate of the FET in order to minimize reflections back into the power combiner. The impedance transforming power combiner reduces component count and associated physical space requirements of the frequency mixing circuit.

Abstract: A low power heterojunction field effect transistor (10, 30, 50, 60) capable of operating at low drain currents while having a low intermodulation distortion. A channel restriction region (9, 38, 51) is formed between the gate electrodes (24, 41, 69) and the drain electrodes (25, 46, 65). The channel restriction region (9, 38, 51) depletes the channel layer (13, 33) thereby constricting a channel and lowering a drain saturation current. The channel restriction region (9, 38, 51) may be used to set a desired drain saturation current such that a second derivative of the transconductance with respect to the gate-source voltage is approximately zero and a first derivative of the transconductance with respect to the gate-source voltage is, approximately, a relative maximum at the desired operating point.

Abstract: A gate-drain shield is used to reduce the gate to drain capacitance of a transistor. The gate-drain shield is formed as a conductor that is positioned on the surface of the transistor between the gate and the drain. The conductor is formed on an insulator thereby electrically insulating the conductor from the substrate of the transistor.