Abstract: Some implementations provide a method for managing data in a storage system that includes a persistent storage device and a non-volatile random access memory (NVRAM) cache device. The method includes: accessing a direct mapping between a logical address associated with data stored on the persistent storage device and a physical address on the NVRAM cache device; receiving, from a host computing device coupled to the storage system, a request to access a particular unit of data stored on the persistent storage device; using the direct mapping as a basis between the logical address associated with the data stored on the persistent storage device and the physical address on the NVRAM cache device to determine whether the particular unit of data being requested is present on the NVRAM cache device.

Abstract: A read writeable random accessible non-volatile memory module includes a printed circuit board with an edge connector that can be plugged into a socket of a printed circuit board. The read writeable random accessible non-volatile memory modules further include a plurality of read writable non-volatile memory devices.

Abstract: In one embodiment of the invention, a server is disclosed including a main printed circuit board; a plurality of processors mounted to the main printed circuit board; and a memory system accessible to the plurality of processors. The memory system includes a plurality of expansion sockets mounted to the printed circuit board, and a plurality of server memory cards removeably plugged into the plurality of expansion sockets. Each server memory card includes a master controller, a plurality of slave controllers, and a plurality of replaceable daughter-memory-cards with read-writeable non-volatile memory.

Abstract: A read writeable random accessible non-volatile memory module includes a printed circuit board with an edge connector that can be plugged into a socket of a printed circuit board. The read writeable random accessible non-volatile memory modules further include a plurality of read writable non-volatile memory devices.

Abstract: A first portion of an asymmetric memory is configured as temporary storage for application data units with sizes corresponding to a small memory block that is smaller than the size of a logical write unit associated with the asymmetric memory. A portion of the remaining asymmetric memory is configured as a reconciled storage for application data units with varying sizes. A first application data unit is received for writing to the asymmetric memory. Based on computing the size of the first application data unit as corresponding to the small memory block, the first application data unit is written to the temporary storage. Upon determining that a threshold is reached, a memory write operation is performed for writing the application data units from the temporary storage to the reconciled storage. The application data units written to the reconciled storage are removed from the temporary storage.

Abstract: Embodiments of the present invention provide systems and methods for recovering a high availability storage system. The storage system includes a first layer and a second layer, each layer including a controller board, a router board, and storage elements. When a component of a layer fails, the storage system continues to function in the presence of a single failure of any component, up to two storage element failures in either layer, or a single power supply failure. While a component is down, the storage system will run in a degraded mode. The passive zone is not serving input/output requests, but is continuously updating its state in dynamic random access memory to enable failover within a short period of time using the layer that is fully operational. When the issue with the failed zone is corrected, a failback procedure brings the system back to a normal operating state.

Abstract: A storage cartridge may include a storage controller comprising a single PCIe port and a PCIe switch. The PCIe switch may include a first PCIe port communicatively coupled to a first PCIe fabric, a second PCIe port communicatively coupled to a second, different PCIe fabric, and a third PCIe port communicatively coupled to the single PCIe port of the storage controller. The first PCIe port and the second PCIe port may be configured to be selectively communicatively coupled to a non-transparent bridge (NTB) of the PCIe switch.

Abstract: A data storage system comprising, a storage device having segments that are configured to store data, and a storage logic coupled to the storage device that manages storage of data on the storage device using a translation table. The storage logic is executable to receive a first marker as part of a backup request, generate a second marker encapsulating a state of the storage device at a second time, calculate a difference between the first marker and the second marker, and generate a backup of data stored in the storage device based on the calculated difference between the first marker and the second marker.

Abstract: By way of example, a data storage system may comprise, a non-transitory storage device storing data blocks in chunks, and a storage logic coupled to the non-transitory storage device that manages storage of data on the storage device. The storage logic is executable to receive a data stream for storage in a non-transitory storage device, the data stream including one or more data blocks, analyze the data stream to determine a domain, retrieve a pre-configured reference set based on the domain, and deduplicate the one or more data blocks of the data stream using the pre-configured reference set.

Abstract: By way of example, a data storage system may comprise a non-transitory storage device storing data blocks in chunks, and a storage logic coupled to the non-transitory storage device that manages storage of data on the storage device. The storage logic is executable to receive a data stream including one or more data blocks, identify a first chunk stored within the non-transitory storage device, retrieve a first local reference set from the first chunk, retrieve a global reference set from the non-transitory storage device, evaluate a performance of the first local reference set and the global reference set, select one of the first local reference set and the global reference set based on the evaluated performance, deduplicate each of the one or more data blocks using the selected reference set, and associate the deduplicated data blocks with the selected reference set.

Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to determine a first value of a first checkpoint associated with a first snapshot, receive a second value of a second checkpoint associated with a translation table entry from an additional source, determine whether the second value of the second checkpoint is after the first value of the first checkpoint, in response to determining that the second value of the second checkpoint is after the first value of the first checkpoint, retrieve the translation table entry associated with the second checkpoint from the additional source, and reconstruct the translation table using the translation table entry associated with the second checkpoint.

Abstract: A method for managing a non-volatile random-access memory (NVRAM)-based storage subsystem, the method including: monitoring, by a slave controller on a NVRAM device of the NVRAM-based storage subsystem, an I/O operation on the NVRAM device; identifying, by the slave controller and based on the monitoring, at least one occurrence of error data; comparing, by the slave controller, a numeric aspect of the at least one occurrence of error data with a threshold setting; reporting, by the slave controller on the NVRAM device and to a master controller of the NVRAM-based storage subsystem, the at least one occurrence of error data in response to the numeric aspect crossing the threshold setting; and ascertaining, by the master controller of the NVRAM-based storage system, a physical location of a defect region on the NVRAM device where the error data has occurred by analyzing the reported at least one occurrence of error data.

Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.

Abstract: Data is stored as a first collection of memory blocks distributed across a first set of memory devices. It is determined that a first memory device in the first set is in a degraded state. Data is recovered corresponding to a first memory block in the first collection of memory blocks that is stored in the first memory device, which is configured to include a first number of memory blocks. The recovered data is stored in a second memory device as a new memory block, which is added to the first collection of memory blocks. The first memory device is removed from the first set and reconfigured with a second number of memory blocks that is less than the first number of memory blocks. Memory blocks in a second collection of memory blocks distributed across a second set of memory devices is stored in the reconfigured first memory device.

Abstract: A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

Abstract: A method for implementing cross device redundancy schemes with a single commit by receiving, by a write page allocation unit, a request to allocate data grains; responsive to receiving the request, performing, by the write page allocation unit, an analysis of a predetermined data layout map associated with a grain memory to identify a memory segment; allocating, by the write page allocation unit, a number of data grains to the memory segment, while computing redundancy data associated with the number of data grains; storing the number of data grains and the redundancy data to the memory segment of the grain memory; determining, by the write page allocation unit, whether a storage threshold associated with the grain memory has been satisfied; and responsive to the storage threshold associated with the grain memory being satisfied, transmitting data grains and redundancy data stored in the memory segment to one or more storage devices.

Abstract: First data is received for storing in a first asymmetric memory device. A first writing phase is identified as a current writing phase. A first segment included in the first asymmetric memory device is identified as next segment available for writing data. The first data is written to the first segment. Information associated with the first segment is stored, along with information indicating that the first segment is written in the first writing phase. Second data is received for storing in the asymmetric memory. A second segment included in the first asymmetric memory device is identified as the next segment available for writing data. The second data is written to the second segment. Information associated with the second segment and the second memory block is stored along with information indicating that the second segment is written in the second writing phase.

Abstract: Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.

Abstract: Metadata that corresponds to application data is distributed across different disruption regions of an asymmetric memory component such that metadata is written in the same disruption region as the application data to which it corresponds. A first block of application data is written to a first disruption region and a second block of application data is written to a second disruption region. A first block of metadata corresponding to the first block of application data and a second block of metadata corresponding to the second block of application data both are generated. The first block of metadata is written to the first disruption region and the second block of metadata is written to the second disruption region such that the first and second blocks of metadata are written to the same disruption regions as the blocks of application data to which they correspond.

Abstract: In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.