Patents by Inventor Vijayakrishna J. Vankayala
Vijayakrishna J. Vankayala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967373Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.Type: GrantFiled: June 2, 2022Date of Patent: April 23, 2024Assignee: Micron Technology, Inc.Inventors: Vijayakrishna J. Vankayala, Hari Giduturi, Jeffrey E. Koelling, Mingdong Cui, Ramachandra Rao Jogu
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Patent number: 11955981Abstract: A memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The memory device further includes multiple die stacked in a three-dimensional stack. A first die of the plurality of die includes a first plurality of memory cells and first local control circuitry. The first local circuitry includes division circuitry configured to receive the clock from the clock input, generate a divided clock having a lower frequency than that of the clock, and generate multiple clocks from the divided clock with each of the multiple clocks having a lower frequency than the divided clock. The memory device also includes one or more transmitters configured to transmit the multiple clocks using a inter-die interconnects between the multiple die.Type: GrantFiled: April 19, 2022Date of Patent: April 9, 2024Assignee: Micron Technology, Inc.Inventor: Vijayakrishna J. Vankayala
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Publication number: 20240070093Abstract: Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The “asymmetric” term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Applicant: Micron Technology, Inc.Inventors: Hyun Yoo Lee, Kang-Yong Kim, Jason McBride Brown, Venkatraghavan Bringivijayaraghavan, Vijayakrishna J. Vankayala
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Patent number: 11887687Abstract: Methods, systems, and devices for read operations for a memory array and register are described. In some examples, a memory device may include one or more memory arrays and one or more registers (e.g., one or more mode registers). The memory device may include circuitry that allows for a command to access a memory array and a command to access a register to be received consecutively (e.g., during consecutive sets of clock cycles). Because the commands may be received during consecutive sets of clock cycles, the corresponding data may also be output from the memory array and register during consecutive clock cycles.Type: GrantFiled: February 23, 2022Date of Patent: January 30, 2024Assignee: Micron Technology, Inc.Inventor: Vijayakrishna J. Vankayala
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Publication number: 20230395565Abstract: Systems, methods, and devices related to techniques for reducing inter-die signal loads within a multi-die package are disclosed. The multi-die package includes a first memory die handling interfacing with a host for the package and at least one second memory die coupled to and configured to communication with the first memory die via an inter-die connection. A technique involves adding an additional wirebond pad to each die in the multi-die package. When the inter-die connections are made, the wirebond pad associated with the first memory die transmitter is connected to the wirebond pad associated with the receiver of a second memory die that is not connected to the transmitter of the second memory die. By not connecting to the transmitter of the second memory die, the first memory die transmits inter-die signals to the second memory die such that a lower signal load is achieved within the multi-die package.Type: ApplicationFiled: August 12, 2022Publication date: December 7, 2023Inventor: Vijayakrishna J. Vankayala
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Publication number: 20230395566Abstract: Systems, methods, and devices related to techniques for repeating inter-die signals within a multi-die package of a memory device are disclosed. The multi-die package includes a memory stack including a first memory die handling interfacing with a host for the package and at least one second memory die coupled to and configured to communicate with the first memory die via an inter-die connection. A technique involves incorporating the use of a multiplexer positioned in front of the transmitter of each die to facilitate repetition of inter-die signals within the memory stack as needed depending on various factors associated with the memory stack, such as, but not limited to, the type of signal, the intended recipient of the inter-die signals, and the stack height of the memory stack.Type: ApplicationFiled: August 12, 2022Publication date: December 7, 2023Inventor: Vijayakrishna J. Vankayala
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Publication number: 20230395145Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.Type: ApplicationFiled: June 2, 2022Publication date: December 7, 2023Inventors: Vijayakrishna J. Vankayala, Hari Giduturi, Jeffrey E. Koelling, Mingdong Cui, Ramachandra Rao Jogu
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Publication number: 20230376432Abstract: Separate inter-die connectors for data and error correction information and related apparatuses, methods, and computing systems are disclosed. An apparatus including a master die, a target die, inter-die data connectors, and inter-die error correction connectors. The target die includes data storage elements. The inter-die data connectors electrically couple the master die to the target die. The inter-die data connectors are configured to conduct write data bits from the master die to the target die. The write data bits are written to the data storage elements. The inter-die error correction connectors electrically couple the master die to the target die. The inter-die error correction connectors are configured to conduct error correction information corresponding to the write data bits from the master die to the target die. The target die includes error correction circuitry configured to generate new error correction information responsive to the write data bits received from the master die.Type: ApplicationFiled: August 4, 2023Publication date: November 23, 2023Inventor: Vijayakrishna J. Vankayala
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Patent number: 11810641Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.Type: GrantFiled: July 10, 2020Date of Patent: November 7, 2023Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, Jennifer E. Taylor, Vijayakrishna J. Vankayala
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Publication number: 20230336181Abstract: A memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The memory device further includes multiple die stacked in a three-dimensional stack. A first die of the plurality of die includes a first plurality of memory cells and first local control circuitry. The first local circuitry includes division circuitry configured to receive the clock from the clock input, generate a divided clock having a lower frequency than that of the clock, and generate multiple clocks from the divided clock with each of the multiple clocks having a lower frequency than the divided clock. The memory device also includes one or more transmitters configured to transmit the multiple clocks using a inter-die interconnects between the multiple die.Type: ApplicationFiled: April 19, 2022Publication date: October 19, 2023Inventor: Vijayakrishna J. Vankayala
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Publication number: 20230335192Abstract: A memory device includes a substrate with two or more memory die stacked in a three-dimensional stacked (3DS) configuration. The memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The two or more memory die each include its own plurality of memory cells. Furthermore, each of the two or more memory die include a local control circuitry configured to receive or transmit a divided clock that is based on the clock.Type: ApplicationFiled: April 19, 2022Publication date: October 19, 2023Inventors: Vijayakrishna J. Vankayala, Hari Giduturi, Jason M. Brown
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Patent number: 11762786Abstract: A memory device including memory cells operating according to a first clock signal having a first clock frequency and accessed based on a data access time. The memory device may include a clock shifter circuit for delaying the access commands based on the data access time. The clock shifter circuitry include a shift register circuit and a phase correction circuit. The shift register circuit delays the access commands using a second clock signal having a fraction of the first clock frequency. The phase correction circuit receives the access commands from the shift register circuitry using the fraction of the first clock frequency, delays the access commands based on phase information of the access commands, and outputs the access commands to the memory cells based on the data access time using the first clock frequency.Type: GrantFiled: August 24, 2021Date of Patent: September 19, 2023Assignee: Micron Technology, Inc.Inventor: Vijayakrishna J. Vankayala
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Patent number: 11755506Abstract: Separate inter-die connectors for data and error correction information and related apparatuses, methods, and computing systems are disclosed. An apparatus including a master die, a target die, inter-die data connectors, and inter-die error correction connectors. The target die includes data storage elements. The inter-die data connectors electrically couple the master die to the target die. The inter-die data connectors are configured to conduct write data bits from the master die to the target die. The write data bits are written to the data storage elements. The inter-die error correction connectors electrically couple the master die to the target die. The inter-die error correction connectors are configured to conduct error correction information corresponding to the write data bits from the master die to the target die. The target die includes error correction circuitry configured to generate new error correction information responsive to the write data bits received from the master die.Type: GrantFiled: June 16, 2022Date of Patent: September 12, 2023Inventor: Vijayakrishna J. Vankayala
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Patent number: 11742008Abstract: A memory device includes a first data driver configured to send according to a first clock signal a first data to a first data port; a second data driver configured to send according to a second clock signal a second data to a second data port, wherein the second clock signal does not match the first clock signal.Type: GrantFiled: April 26, 2021Date of Patent: August 29, 2023Assignee: Micron Technology, Inc.Inventors: Jason M. Brown, Vijayakrishna J. Vankayala, Todd A. Dauenbaugh
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Publication number: 20230267974Abstract: Methods, systems, and devices for read operations for a memory array and register are described. In some examples, a memory device may include one or more memory arrays and one or more registers (e.g., one or more mode registers). The memory device may include circuitry that allows for a command to access a memory array and a command to access a register to be received consecutively (e.g., during consecutive sets of clock cycles). Because the commands may be received during consecutive sets of clock cycles, the corresponding data may also be output from the memory array and register during consecutive clock cycles.Type: ApplicationFiled: February 23, 2022Publication date: August 24, 2023Inventor: Vijayakrishna J. Vankayala
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Patent number: 11727979Abstract: Methods of operating a memory device are disclosed. A method may include asserting, at a semiconductor device, an internal signal in response to receipt of a command. The method may also include holding the internal signal in an asserted state for at least a predetermined time duration upon assertion of the internal signal. Further, the method may include generating an enable signal based on the internal signal and a clock signal. Associated devices and systems are also disclosed.Type: GrantFiled: July 7, 2021Date of Patent: August 15, 2023Assignee: Micron Technology, Inc.Inventors: Kallol Mazumder, Navya Sri Sreeram, William C. Waldrop, Vijayakrishna J. Vankayala
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Patent number: 11705429Abstract: A device may include a first die having a first circuit and a second die having a second circuit. The die may be separated by a material layer. The material layer may include multiple through-silicon vias (TSVs) for electrically coupling the first die to the second die. A first TSV of the TSVs may electrically couple the first circuit to the second circuit and a second TSV of the TSVs may include a redundant TSV that electrically bypasses the first TSV to couple the first circuit to the second circuit if a fault is detected in the first TSV.Type: GrantFiled: September 4, 2020Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Jason M. Brown, Vijayakrishna J. Vankayala
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Publication number: 20230068313Abstract: A memory device including memory cells operating according to a first clock signal having a first clock frequency and accessed based on a data access time. The memory device may include a clock shifter circuit for delaying the access commands based on the data access time. The clock shifter circuitry include a shift register circuit and a phase correction circuit. The shift register circuit delays the access commands using a second clock signal having a fraction of the first clock frequency. The phase correction circuit receives the access commands from the shift register circuitry using the fraction of the first clock frequency, delays the access commands based on phase information of the access commands, and outputs the access commands to the memory cells based on the data access time using the first clock frequency.Type: ApplicationFiled: August 24, 2021Publication date: March 2, 2023Inventor: Vijayakrishna J. Vankayala
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Publication number: 20230007872Abstract: Methods of operating a memory device are disclosed. A method may include asserting, at a semiconductor device, an internal signal in response to receipt of a command. The method may also include holding the internal signal in an asserted state for at least a predetermined time duration upon assertion of the internal signal. Further, the method may include generating an enable signal based on the internal signal and a clock signal. Associated devices and systems are also disclosed.Type: ApplicationFiled: July 7, 2021Publication date: January 12, 2023Inventors: Kallol Mazumder, Navya Sri Sreeram, William C. Waldrop, Vijayakrishna J. Vankayala
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Patent number: 11487610Abstract: Systems and methods are described, in which a parity error alert timing interlock is provided by first waiting for a timer to count a configured parity error pulse width value and then waiting for any in-progress memory operations to complete before deasserting a parity error alert signal that was asserted in response to the detection of a parity error in a command or address.Type: GrantFiled: May 9, 2018Date of Patent: November 1, 2022Assignee: Micron Technology, Inc.Inventors: William C. Waldrop, Vijayakrishna J. Vankayala, Scott E. Smith