Abstract: Exemplary embodiments are directed to devices and method for operating a charge pump. A method may include activating a first switch coupled between a capacitor and a ground voltage over a first period of a charging phase. The first period may coincide with a non-overlapping time between the charging phase and an output phase. The method may also include activating a second switch coupled between the capacitor and an input voltage over a second period of the charging phase, wherein the first period begins prior to the second period. Further, the method may include deactivating the second switch over a third period of the charging phase and deactivating the first switch over a fourth period of the charging phase, wherein the third period begins prior to the fourth period.

Abstract: A low voltage multi-stage amplifier is described. The low voltage multi-stage amplifier includes one or more prior stages. The low voltage multi-stage amplifier also includes a supply stage. The low voltage multi-stage amplifier further includes an output stage that operates with a supply voltage as low as a sum of a threshold voltage of a first transistor in the output stage and a saturation voltage of a second transistor of the supply stage. The supply stage supplies the output stage.

Abstract: An amplifier with high power supply rejection is disclosed. In an exemplary implementation, an amplifier includes a first stage configured to receive a signal to be amplified, a second stage comprising an input transistor coupled to the first stage, and further comprising at least one additional transistor, and a voltage regulator configured to received a first supply voltage and generate a regulated supply voltage, the first supply voltage coupled to the at least one additional transistor, the regulated supply voltage coupled to the first stage and the input transistor of the second stage to improve power supply noise rejection of the apparatus.

Abstract: A variable supply rail generator is described. The variable supply rail generator includes a regulator configured to use an estimated load current for a power amplifier to optimize efficiency. The variable supply rail generator also includes a power amplifier controller. The power amplifier controller provides the estimated load current to the regulator.

Abstract: Disclosed are systems and methods for suppressing voltage peaking in a buck regulator. In one aspect, a buck regulator comprises: a pulse-width modulator (PWM) that generates a pulsed signal; a switch operable to selectively connect the regulator to a DC power supply in response to the pulsed signal and output a pulsed output DC signal; a filter for filtering out high frequency noise from the pulsed output DC signal and generating a regulated output signal; an integrator for comparing the pulsed output DC signal with a reference voltage signal and generating an error signal for input to the PWM; a subtractor operable to subtract the reference voltage signal from the filtered output signal to generate an error feedback signal; and an adder operable to add the error feedback signal to the error signal for input to the pulse-width modulator in order to suppress voltage peaks in the filtered output signal.

Abstract: Techniques for applying waveform shaping to DC-to-DC level transitions in an audio amplifier. In an aspect, a waveform shaping block may utilize a non-linear shaping waveform such as a Gaussian waveform, raised-cosine waveform, root-raised cosine waveform, etc., to shape the transition between two DC levels in an audio amplifier output. The waveform shaping techniques may be utilized, e.g., during power-up or power-down of the amplifier, or in an impedance measurement mode, to reduce audio artifacts associated with the transition while minimizing overall transition time.

Abstract: An amplifier with high power supply rejection is disclosed. In an exemplary implementation, an amplifier includes a first stage configured to receive a signal to be amplified, a second stage comprising an input transistor coupled to the first stage, and further comprising at least one additional transistor, and a voltage regulator configured to received a first supply voltage and generate a regulated supply voltage, the first supply voltage coupled to the at least one additional transistor, the regulated supply voltage coupled to the first stage and the input transistor of the second stage to improve power supply noise rejection of the apparatus.

Abstract: An amplifier with improved noise reduction is disclosed. In one implementation, an amplifier is provided that includes a main output stage configured to output an amplified signal at a main output terminal, a secondary output stage configured to output a copy of the amplified signal at a secondary output terminal, and a signal coupler configured to provide a variable resistance coupling between the secondary output terminal and the main output terminal to reduce noise at the main output terminal.

Abstract: Techniques for generating a bias voltage for a class AB amplifier having first and second active transistors. In an exemplary embodiment, a diode-coupled first transistor supports a first current, and the gate voltage of the first transistor is coupled to the gate voltage of the first active transistor. The first current is split into a second current and a first auxiliary current supported by a second transistor, which is biased at a desired common-mode output voltage of the class AB amplifier. The first auxiliary current is further combined with a third current to be supported by a third transistor, with the third transistor configured to replicate the characteristic of the second active transistor. Further techniques are provided for setting the drain voltage of the third transistor to be close to the common-mode output voltage. The techniques described herein may be used to provide a bias voltage for the NMOS and/or PMOS active transistors in a class AB amplifier.

Abstract: The invention includes methods and systems for providing a multi-path common mode feedback loop in an amplifier system. Embodiments include techniques for dividing a common mode feedback current path to provide a slow common mode feedback current path and a fast common mode feedback current path. The slow and fast paths are configured for controlling common mode feedback current within a small bandwidth.

Abstract: A differential amplifier circuit which amplifies a signal developed by a signal generating device when coupled between first and second input nodes and provides an amplified differential signal at first and second output nodes. First and second current sources source first and second current levels to the first input node and the first output node, respectively. First and second current sinks sink the first and second current levels from the second input node and the second output node, respectively. A first current amplifier controls current between the first output node and the second input node to maintain the second input node at a first bias voltage level. A second current amplifier controls current between the first input node and the second output node to maintain the first input node at a second bias voltage level. An optional feedback circuit senses a DC offset and adjusts current to compensate.

Abstract: The invention includes methods and systems for providing a multi-path common mode feedback loop in an amplifier system. Embodiments include techniques for dividing a common mode feedback current path to provide a slow common mode feedback current path and a fast common mode feedback current path. The slow and fast paths are configured for controlling common mode feedback current within a small bandwidth.

Abstract: A negative current generator for an amplifier circuit including a shunt transistor, first and second mirror transistors, a current bias device, and an amplifier. The amplifier circuit includes a current source transistor having current terminals coupled between a supply terminal and an input node and a control terminal receiving a bias voltage. The shunt transistor is coupled in a shunt configuration with the current source transistor. Each mirror transistor has a control terminal, a first current terminal coupled to the supply terminal and a second terminal coupled to a voltage node. The control terminal of the first mirror transistor receives another bias voltage. The current bias device draws a constant current from the voltage node. The amplifier has a first input receiving a reference voltage, a second input coupled to the voltage node, and an output coupled to the control terminals of the shunt and second mirror transistors.

Abstract: Multiple fuse circuits are used associated with a corresponding number of bits forming a desired value which may need to be stored in a non-volatile storage. Assuming the desired value contains a first count number of zeros and a second count number of ones, the fuse circuits at bit positions having values equaling the logical value with smaller count are blown. If the blown fuse circuits generate the logical value associated with larger one of the two counts, the outputs of all the fuse circuits are inverted. Thus, a desired value can be always generated while reducing the number of fuse circuits blown.

Abstract: Multiple fuse circuits are used associated with a corresponding number of bits forming a desired value which may need to be stored in a non-volatile storage. Assuming the desired value contains a first count number of zeros and a second count number of ones, the fuse circuits at bit positions having values equaling the logical value with smaller count are blown. If the blown fuse circuits generate the logical value associated with larger one of the two counts, the outputs of all the fuse circuits are inverted. Thus, a desired value can be always generated while reducing the number of fuse circuits blown.