Patents by Inventor Vijayakumar S

Vijayakumar S has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7268015
    Abstract: A method for wafer stacking employing substantially uniform copper structures is described herein.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: September 11, 2007
    Assignee: Intel Corporation
    Inventors: Vijayakumar S. RamachandraRao, Shriram Ramanathan
  • Patent number: 7238604
    Abstract: A thin hard mask is formed over a semiconductor substrate. The thin hard mask allows diffusion of a sacrificial material or pore-forming agent therethrough to form an underlying air gap or porous dielectric region. The thin hard mask may be a polymer or an initially porous material that may be later densified. The thin hard mask may be used to prevent etch steps used in forming an unlanded via from reaching layers below the hard mask.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: July 3, 2007
    Assignee: Intel Corporation
    Inventors: Grant M. Kloster, Kevin P. O'Brien, David H. Gracias, Hyun-Mog Park, Vijayakumar S. Ramachandrarao
  • Patent number: 7233068
    Abstract: Suitable particles may be deposited within an extremely small high-aspect ratio via by flowing the particles in a suspension using supercritical carbon dioxide. The particles may be made up of diblock copolymers or silesquioxane-based materials or oligomers of phobic homopolymers or pre-formed silica-based particles stabilized using diblock copolymers and may include chemical initiators to permit in situ polymerization within the via.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: June 19, 2007
    Assignee: Intel Corporation
    Inventors: Vijayakumar S. Ramachandrarao, Robert B. Turkot, Jr.
  • Patent number: 7220668
    Abstract: A method of patterning a porous dielectric material that includes an ash process to treat the porous dielectric material. The treated porous dielectric material allows for the formation of a substantially continuous barrier layer, which can inhibit diffusion of, for example, a conductive material into to the dielectric material. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventors: Hyun-Mog Park, Boyan Boyanov, Grant M. Kloster, Vijayakumar S. RamachandraRao
  • Patent number: 7179757
    Abstract: Processing problems associated with porous low-k dielectric materials are often severe. Exposure of low-k materials to plasma during feature etching, ashing, and priming steps has deleterious consequences. For porous, silicon-based low-k dielectric materials, the plasma depletes a surface organic group, raising the dielectric constant of the material. In the worst case, the damaged dielectric is destroyed during the wet etch removal of the antireflective coating in the via-first copper dual-damascene integration scheme. This issue is addressed by exposing the dielectric to silane coupling agents at various stages of etching and cleaning. Chemical reactions with the silane coupling agent both replenish the dielectric surface organic group and passivate the dielectric surface relative to the surface of the antireflective coating.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventors: Vijayakumar S. RamachandraRao, David H. Gracias
  • Patent number: 7101443
    Abstract: Supercritical carbon dioxide may be utilized to clean metal lines (e.g. copper, cobalt). The supercritical carbon dioxide cleans may include hydrogen gas in one embodiment, hydrofluoric acid in another embodiment, and hexafluoroacetyl acetone as a metal-binding ligand in another embodiment.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventor: Vijayakumar S. Ramachandrarao
  • Patent number: 7038324
    Abstract: Wafer stacking employing substantially uniform copper structures is described herein.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: May 2, 2006
    Assignee: Intel Corporation
    Inventors: Vijayakumar S. RamachandraRao, Shriram Ramanathan
  • Patent number: 7022655
    Abstract: Supercritical carbon dioxide may be utilized to remove resistant residues such as those residues left when etching dielectrics in fluorine-based plasma gases. The supercritical carbon dioxide may include an ionic liquid in one embodiment.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: April 4, 2006
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Robert B. Turkot, Jr., Vijayakumar S. Ramachandrarao
  • Patent number: 7018938
    Abstract: Radiant energy may be applied to a photochemically susceptible etching or conditioning solution to enable precise control of the removal of material or alteration of the top surface of a wafer during the fabrication of semiconductor integrated circuits. A particular condition may be detected during the course of photoactivated generation of free radicals or molecular activation to control the further generation of said species by controlling the radiant energy exposure of a wafer.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: March 28, 2006
    Assignee: Intel Corporation
    Inventors: Subramanyam A. Iyer, Justin K. Brask, Vijayakumar S. Ramachandrarao
  • Patent number: 7005390
    Abstract: Processing problems associated with porous low-k dielectric materials are often severe. Exposure of low-k materials to plasma during feature etching, ashing, and priming steps has deleterious consequences. For porous, silicon-based low-k dielectric materials, the plasma depletes a surface organic group, raising the dielectric constant of the material. In the worst case, the damaged dielectric is destroyed during the wet etch removal of the antireflective coating in the via-first copper dual-damascene integration scheme. This issue is addressed by exposing the dielectric to silane coupling agents at various stages of etching and cleaning. Chemical reactions with the silane coupling agent both replenish the dielectric surface organic group and passivate the dielectric surface relative to the surface of the antireflective coating.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventors: Vijayakumar S. RamachandraRao, David H. Gracias
  • Patent number: 6974762
    Abstract: A method of silanizing the surface of a low-k interlayer dielectric oxides (carbon doped oxides or organo-silicate glasses) to improve surface adhesion to adjacent thin film layers in damascene integration of microelectronic devices. A low-k interlayer dielectric oxide may be exposed to the vapor of a silane-coupling agent in order to modify its surface energy to improve adhesion with adjacent thin film layers. A low-k interlayer dielectric oxide can also be silanized by dipping the low-k interlayer dielectric oxide in a solution of silane-coupling agent. The silane-coupling agent will cause covalent bonds between the low-k interlayer dielectric oxide and the adjacent thin film thereby improving adhesion.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: David H. Gracias, Vijayakumar S. Ramachandrarao
  • Publication number: 20040261816
    Abstract: Bidentate chelating ligands may be utilized to remove metal contaminants in semiconductor wafers. Each metal center may have three chelating ligands attached to it. The resulting complex may be removed as a vapor using a dynamic vacuum or a supercritical carbon dioxide, as two examples.
    Type: Application
    Filed: June 27, 2003
    Publication date: December 30, 2004
    Inventors: Justin K. Brask, Vijayakumar S. Ramachandrarao
  • Publication number: 20040266184
    Abstract: A method for modifying an interlayer dielectric (ILD) is disclosed. In one embodiment, an ILD is formed having metallization therein, which may have a protective layer. The ILD is then exposed to a first solution comprising a F− ion, either aqueous with a co-solvent or an organic-HF in conjunction with an organic solvent in supercritical carbon dioxide. After exposing the ILD to the first solution, the ILD is exposed to a second solution comprising a silane in supercritical carbon dioxide. In another embodiment, the ILD is exposed to the first solution after a damascene process including a chemical mechanical polishing is performed on the ILD. In a further embodiment, the ILD can be polymerized to create an organic polymer network after the ILD has been exposed to the second solution.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Vijayakumar S. RamachandraRao, Kevin P. O'brien
  • Patent number: 6812132
    Abstract: Suitable particles may be deposited within an extremely small high-aspect ratio via by flowing the particles in a suspension using supercritical carbon dioxide. The particles may be made up of diblock copolymers or silesquioxane-based materials or oligomers of phobic homopolymers or pre-formed silica-based particles stabilized using diblock copolymers and may include chemical initiators to permit in situ polymerization within the via.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: November 2, 2004
    Assignee: Intel Corporation
    Inventors: Vijayakumar S. Ramachandrarao, Robert B. Turkot, Jr.
  • Publication number: 20040214427
    Abstract: A thin hard mask is formed over a semiconductor substrate. The thin hard mask allows diffusion of a sacrificial material or pore-forming agent therethrough to form an underlying air gap or porous dielectric region. The thin hard mask may be a polymer or an initially porous material that may be later densified. The thin hard mask may be used to prevent etch steps used in forming an unlanded via from reaching layers below the hard mask.
    Type: Application
    Filed: April 24, 2003
    Publication date: October 28, 2004
    Inventors: Grant M. Kloster, Kevin P. O'Brien, David H. Gracias, Hyun-Mog Park, Vijayakumar S. Ramachandrarao
  • Publication number: 20040185656
    Abstract: Suitable particles may be deposited within an extremely small high-aspect ratio via by flowing the particles in a suspension using supercritical carbon dioxide. The particles may be made up of diblock copolymers or silesquioxane-based materials or oligomers of phobic homopolymers or pre-formed silica-based particles stabilized using diblock copolymers and may include chemical initiators to permit in situ polymerization within the via.
    Type: Application
    Filed: March 21, 2003
    Publication date: September 23, 2004
    Inventors: Vijayakumar S. Ramachandrarao, Robert B. Turkot,
  • Publication number: 20040171502
    Abstract: Supercritical carbon dioxide may be utilized to remove resistant residues such as those residues left when etching dielectrics in fluorine-based plasma gases. The supercritical carbon dioxide may include an oxidizer in one embodiment.
    Type: Application
    Filed: February 28, 2003
    Publication date: September 2, 2004
    Inventors: Shan C. Clark, Vijayakumar S. Ramachandrarao, Robert B. Turkot
  • Publication number: 20040147419
    Abstract: Supercritical carbon dioxide may be utilized to clean metal lines (e.g. copper, cobalt). The supercritical carbon dioxide cleans may include hydrogen gas in one embodiment, hydrofluoric acid in another embodiment, and hexafluoroacetyl acetone as a metal-binding ligand in another embodiment.
    Type: Application
    Filed: January 29, 2003
    Publication date: July 29, 2004
    Inventor: Vijayakumar S. Ramachandrarao
  • Publication number: 20040134885
    Abstract: Liquid phase co-solvent(s) may be combined with supercritical carbon dioxide for more effective use of wet chemistries for cleaning and etching applications in semiconductor fabrication technologies. Because of the use of the two-phase system, more effective solvents, for example that may not be completely soluble in supercritical carbon dioxide, may be utilized, and the benefits of both the supercritical carbon dioxide gas-like phase and the liquid co-solvent may be achieved, in some cases. The efficacy of supercritical carbon dioxide cleaning can be enhanced by repetition of the etch/clean steps on the substrate, sometimes in conjunction with intervening rinse steps.
    Type: Application
    Filed: January 14, 2003
    Publication date: July 15, 2004
    Inventors: Subramanyam A. Iyer, Vijayakumar S. Ramachandrarao, Robert B. Turkot
  • Publication number: 20040097076
    Abstract: Radiant energy may be applied to a photochemically susceptible etching or conditioning solution to enable precise control of the removal of material or alteration of the top surface of a wafer during the fabrication of semiconductor integrated circuits. A particular condition may be detected during the course of photoactivated generation of free radicals or molecular activation to control the further generation of said species by controlling the radiant energy exposure of a wafer.
    Type: Application
    Filed: November 14, 2002
    Publication date: May 20, 2004
    Inventors: Subramanyam A. Iyer, Justin K. Brask, Vijayakumar S. Ramachandrarao