Patents by Inventor Viju K. Mathews
Viju K. Mathews has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7398595Abstract: An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.Type: GrantFiled: July 17, 2006Date of Patent: July 15, 2008Assignee: Micron Technology, Inc.Inventors: Pierre C. Fazan, Viju K. Mathews
-
Patent number: 7393753Abstract: Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the electrode in a lower region of a substrate opening. The method may further include forming a second portion of the electrode in the opening and overlying the first portion, the insulative layer encompassing a sidewall of the second portion. The method may further include forming a third portion of the electrode overlying the second portion and overlying at least a portion of the insulative layer, wherein the first portion and the second portion are different materials. In an embodiment, the second portion is a diffusion barrier layer and the third portion is an oxidation resistant layer. In an embodiment, the method includes encompassing a lower sidewall of the third portion with the insulative layer.Type: GrantFiled: March 21, 2007Date of Patent: July 1, 2008Assignee: Micron Technology, Inc.Inventors: Pierre C. Fazan, Viju K. Mathews
-
Patent number: 7385240Abstract: An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.Type: GrantFiled: March 8, 2006Date of Patent: June 10, 2008Assignee: Micron Technology, Inc.Inventors: Pierre C. Fazan, Viju K. Mathews
-
Patent number: 7253052Abstract: Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the electrode in a lower region of a substrate opening. The method may further include forming a second portion of the electrode in the opening and overlying the first portion, the insulative layer encompassing a sidewall of the second portion. The method may further include forming a third portion of the electrode overlying the second portion and overlying at least a portion of the insulative layer, wherein the first portion and the second portion are different materials. In an embodiment, the second portion is a diffusion barrier layer and the third portion is an oxidation resistant layer. In an embodiment, the method includes encompassing a lower sidewall of the third portion with the insulative layer.Type: GrantFiled: July 22, 2004Date of Patent: August 7, 2007Assignee: Micron Technology, Inc.Inventors: Pierre C. Fazan, Viju K. Mathews
-
Patent number: 7153707Abstract: An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.Type: GrantFiled: September 13, 2004Date of Patent: December 26, 2006Assignee: Micron Technology, Inc.Inventors: Pierre C. Fazan, Viju K. Mathews
-
Patent number: 6835634Abstract: A field isolation process performed on a silicon wafer is carried out by high pressure oxidation. Using oxygen rather than water vapor as the oxidant substantially eliminates nitride inclusions via the Kooi effect. Preferred high pressure field oxidation processes simplify all CMOS flows by eliminating the need for sacrificial oxide growth and removal steps.Type: GrantFiled: March 10, 1998Date of Patent: December 28, 2004Assignee: Micron Technology, Inc.Inventors: Pierre C. Fazan, Viju K. Mathews, Nanseng Jeng
-
Patent number: 6791131Abstract: The invention is a storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewall of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layer is formed in the recess and the top surface of the barrier layer is recessed below the top surface of the oxide or oxide/nitride layer. The process continued with a formation of an oxidation resistant conductive layer and the deposition of a further oxide layer to fill remaining portions of the recess.Type: GrantFiled: January 24, 2000Date of Patent: September 14, 2004Assignee: Micron Technology, Inc.Inventors: Pierre C. Fazan, Viju K. Mathews
-
Patent number: 6762475Abstract: A method of forming isolation structures in semiconductor substrates comprising exposing a region of the semiconductor simultaneously to a transforming agent and to a viscosity reducing agent so that the transforming agent transforms a portion of the substrate into an isolation structure and the viscosity reducing agent reduces the viscosity of the isolation structure during formation. In one embodiment, a silicon substrate is exposed to oxygen in the presence of fluorine so that a silicon oxide isolation region is formed. The fluorine reduces the viscosity of the silicon oxide isolation region during formation which results in less lateral, bird's beak encroachment under adjacent masking stacks and also results in lower internal stress in the isolation region during formation. The lower internal stress and the lessened lateral encroachment result in thicker and improved isolation regions.Type: GrantFiled: June 12, 2003Date of Patent: July 13, 2004Assignee: Micron Technology, Inc.Inventors: Viju K. Mathews, Nanseng Jeng, Pierre C. Fazan
-
Publication number: 20030218232Abstract: A method of forming isolation structures in semiconductor substrates comprising exposing a region of the semiconductor simultaneously to a transforming agent and to a viscosity reducing agent so that the transforming agent transforms a portion of the substrate into an isolation structure and the viscosity reducing agent reduces the viscosity of the isolation structure during formation. In one embodiment, a silicon substrate is exposed to oxygen in the presence of fluorine so that a silicon oxide isolation region is formed. The fluorine reduces the viscosity of the silicon oxide isolation region during formation which results in less lateral, bird's beak encroachment under adjacent masking stacks and also results in lower internal stress in the isolation region during formation. The lower internal stress and the lessened lateral encroachment result in thicker and improved isolation regions.Type: ApplicationFiled: June 12, 2003Publication date: November 27, 2003Inventors: Viju K. Mathews, Nanseng Jeng, Pierre C. Fazan
-
Patent number: 6611038Abstract: A method of forming isolation structures in semiconductor substrates comprising exposing a region of the semiconductor simultaneously to a transforming agent and to a viscosity reducing agent so that the transforming agent transforms a portion of the substrate into an isolation structure and the viscosity reducing agent reduces the viscosity of the isolation structure during formation. In one embodiment, a silicon substrate is exposed to oxygen in the presence of fluorine so that a silicon oxide isolation region is formed. The fluorine reduces the viscosity of the silicon oxide isolation region during formation which results in less lateral, bird's beak encroachment under adjacent masking stacks and also results in lower internal stress in the isolation region during formation. The lower internal stress and the lessened lateral encroachment result in thicker and improved isolation regions.Type: GrantFiled: December 19, 2001Date of Patent: August 26, 2003Assignee: Micron Technology, Inc.Inventors: Viju K. Mathews, Nanseng Jeng, Pierre C. Fazan
-
Patent number: 6465326Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. A mass of material is formed over at least a portion of the bird's beak region. In a preferred implementation, the mass of material is formed from material which is different than the material from which the oxidation mask and the field oxide region are formed. According to one aspect of the invention, the material comprises, polysilicon. In another preferred implementation, such different material comprises a spacer which is formed over at least a portion of the oxidation mask. Preferably, an undercut region is formed under the mass or spacer and subsequently filled with oxide material.Type: GrantFiled: May 14, 2001Date of Patent: October 15, 2002Assignee: Micron Technology, Inc.Inventor: Viju K. Mathews
-
Patent number: 6429525Abstract: Formation of a structure of a conductive layer of an integrated circuit includes providing a conductive layer to be patterned and then forming a titanium nitride layer on the conductive layer. An oxide region is formed on the titanium nitride layer. A photoresist layer is formed oh the oxide region for use in patterning the conductive layer. The oxide region may be formed by oxidation of the titanium nitride layer or by depositing an oxide layer on the titanium nitride layer.Type: GrantFiled: February 1, 2001Date of Patent: August 6, 2002Assignee: Micron Technology, Inc.Inventor: Viju K. Mathews
-
Publication number: 20020060355Abstract: A method of forming isolation structures in semiconductor substrates comprising exposing a region of the semiconductor simultaneously to a transforming agent and to a viscosity reducing agent so that the transforming agent transforms a portion of the substrate into an isolation structure and the viscosity reducing agent reduces the viscosity of the isolation structure during formation. In one embodiment, a silicon substrate is exposed to oxygen in the presence of fluorine so that a silicon oxide isolation region is formed. The fluorine reduces the viscosity of the silicon oxide isolation region during formation which results in less lateral, bird's beak encroachment under adjacent masking stacks and also results in lower internal stress in the isolation region during formation. The lower internal stress and the lessened lateral encroachment result in thicker and improved isolation regions.Type: ApplicationFiled: December 19, 2001Publication date: May 23, 2002Inventors: Viju K. Mathews, Nanseng Jeng, Pierre C. Fazan
-
Patent number: 6365490Abstract: A method of forming isolation structures in semiconductor substrates comprising exposing a region of the semiconductor simultaneously to a transforming agent and to a viscosity reducing agent so that the transforming agent transforms a portion of the substrate into an isolation structure and the viscosity reducing agent reduces the viscosity of the isolation structure during formation. In one embodiment, a silicon substrate is exposed to oxygen in the presence of fluorine so that a silicon oxide isolation region is formed. The fluorine reduces the viscosity of the silicon oxide isolation region during formation which results in less lateral, bird's beak encroachment under adjacent masking stacks and also results in lower internal stress in the isolation region during formation. The lower internal stress and the lessened lateral encroachment result in thicker and improved isolation regions.Type: GrantFiled: February 11, 1999Date of Patent: April 2, 2002Assignee: Micron Technology, Inc.Inventors: Viju K. Mathews, Nanseng Jeng, Pierre C. Fazan
-
Publication number: 20010029085Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. A mass of material is formed over at least a portion of the bird's beak region. In a preferred implementation, the mass of material is formed from material which is different than the material from which the oxidation mask and the field oxide region are formed. According to one aspect of the invention, the material comprises polysilicon. In another preferred implementation, such different material comprises a spacer which is formed over at least a portion of the oxidation mask. Preferably, an undercut region is formed under the mass or spacer and subsequently filled with oxide material.Type: ApplicationFiled: May 14, 2001Publication date: October 11, 2001Inventor: Viju K. Mathews
-
Publication number: 20010018257Abstract: A method for use in patterning a conductive layer of an integrated circuit includes providing a conductive layer to be patterned and then forming a titanium nitride layer on the conductive layer. An oxide region is formed on the titanium nitride layer. A photoresist layer is formed on the oxide region for use in patterning the conductive layer. The oxide region may be formed by oxidation of the titanium nitride layer or by depositing an oxide layer on the titanium nitride layer.Type: ApplicationFiled: February 1, 2001Publication date: August 30, 2001Applicant: Micron Technology, Inc.Inventor: Viju K. Mathews
-
Patent number: 6245671Abstract: A semiconductor processing method of forming an electrically conductive contact plug relative to a wafer includes, a) providing a substrate to which electrical connection is to be made; b) depositing a layer of first material atop the substrate to a selected thickness; c) pattern masking the first material layer for formation of a desired contact opening therethrough; d) etching through the first material layer to form a contact opening therethrough for making electrical connection with the substrate, the contact opening having an outermost region; e) after etching to form the contact opening, removing the masking from the first material layer; f) after removing the masking from the first material layer, facet sputter etching into the first material layer relative to the contact opening to provide outwardly angled sidewalls which effectively widen the contact opening outermost region, the outwardly angled sidewalls having an inner base where they join with the original contact opening; g) depositing a layer oType: GrantFiled: February 1, 1999Date of Patent: June 12, 2001Assignee: Micron Technology, Inc.Inventors: Viju K. Mathews, Nanseng Jeng, Pierre C. Fazan
-
Patent number: 6245644Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. A mass of material is formed over at least a portion of the bird's beak region. In a preferred implementation, the mass of material is formed from material which is different than the material from which the oxidation mask and the field oxide region are formed. According to one aspect of the invention, the material comprises polysilicon. In another preferred implementation, such different material comprises a spacer which is formed over at least a portion of the oxidation mask. Preferably, an undercut region is formed under the mass or spacer and subsequently filled with oxide material.Type: GrantFiled: April 6, 1999Date of Patent: June 12, 2001Assignee: Micron Technology, Inc.Inventor: Viju K. Mathews
-
Patent number: 6211078Abstract: A method for use in patterning a conductive layer of an integrated circuit includes providing a conductive layer to be patterned and then forming a titanium nitride layer on the conductive layer. An oxide region is formed on the titanium nitride layer. A photoresist layer is formed on the oxide region for use in patterning the conductive layer. The oxide region may be formed by oxidation of the titanium nitride layer or by depositing an oxide layer on the titanium nitride layer.Type: GrantFiled: August 18, 1997Date of Patent: April 3, 2001Assignee: Micron Technology, Inc.Inventor: Viju K. Mathews
-
Patent number: 6156612Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked by the oxidation mask. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. In accordance with a first implementation, a portion of the semiconductive substrate is removed after removal of the oxidation mask but before the formation and removal of a sacrificial oxide layer. In accordance with this implementation, removal of the semiconductive substrate material forms an undercut region under the bird's beak region which is subsequently filled in with material when the sacrificial oxide layer is formed. In accordance with a second implementation, a portion of the semiconductive substrate is removed after formation and removal of the sacrificial oxide layer.Type: GrantFiled: November 2, 1999Date of Patent: December 5, 2000Assignee: Micron Technology, Inc.Inventor: Viju K. Mathews