Abstract: The method of the present invention introduces a fabrication method for forming a storage capacitor on a supporting silicon substrate of a semiconductor device, by the steps of: forming a bottom capacitor electrode comprising conductively doped polysilicon; forming an insulating layer over the bottom electrode via a first rapid thermal processing step (RTP) using rapid thermal silicon nitride (RTN); forming a capacitor dielectric material comprising tantalum oxide (Ta.sub.2 O.sub.5) over the insulating layer; forming a semiconductive layer comprising polysilicon over the capacitor dielectric material; converting the semiconductive layer into a reaction prevention barrier by subjecting the semiconductive layer to a second rapid thermal processing step (RTP) using rapid thermal silicon nitride (RTN); and forming a top capacitor conductive electrode comprising titanium nitride (TiN) over the reaction prevention barrier.

Abstract: Described is a process used during the formation of a semiconductor device to produce a doped layer of polycrystalline silicon having a pair of conductivity types using a single mask step. In a first embodiment, a patterned nonoxidizing layer is formed over the layer of polycrystalline silicon thereby leaving protected and exposed poly. The exposed polycrystalline silicon is doped, then oxidized, with the protected poly being free of oxidation. The nonoxidizing layer is stripped, and a blanket implant is performed. The oxidation prevents the previously doped polycrystalline silicon from being counterdoped. The oxidation is then stripped and wafer processing continues. In a second embodiment, a layer of resist is formed over the polycrystalline silicon layer, and the exposed poly is heavily doped with a material having a first conductivity type. The resist is removed, and the surface is blanket doped with a material having a second conductivity type.

Abstract: A pad oxide is formed on a silicon substrate followed by a layer of polysilicon about 100 .ANG. thick. A silicon nitride layer is formed over said polysilicon layer then patterned with a first, fluorine-based, etch process to expose selected areas of the polysilicon layer. Then the exposed areas of polysilicon are removed using a second, chlorine-based, etch process fundamentally different from the first etch process. The high selectivity of the first etch process for nitride combined with the high selectivity of the second etch process for oxide, results in negligible CD loss in the overall process.

Abstract: A method of forming a capacitor in semiconductor water processing comprising the following steps: a) providing a conductively doped first layer of polysilicon atop a silicon wafer to a first thickness; b) depositing an undoped second layer of polysilicon over the conductively doped first layer of polysilicon to a second thickness, the layer of undoped polysilicon being deposited at a deposition temperature of at least 590.degree. and having an upper surface; c) impinging laser energy onto the upper surface of the second polysilicon layer at a laser fluence of 0.3 J/cm.sup.2 or greater to roughen the upper surface and thereby increase the capacitance of the second polysilicon layer; d) patterning and etching the first and second polysilicon layers to define a lower capacitor plate; e) providing a layer of capacitor dielectric atop the roughened second polysilicon layer upper surface; and f) providing a layer of conductive material atop the capacitor dielectric to define an upper capacitor plate.