Abstract: An electrical component is formed with a directed self assembly portion having a random electrical characteristic, such as resistance or capacitance. The random pattern can be produced by using a directed self assembly polymer with guide structures 2 including randomness inducing features. The electrical components with the random electrical characteristics may be used in electrical circuits relying upon random variation in electrical characteristics, such as physically unclonable function circuitry. The electrical components may be resistors and/or capacitors.

Abstract: A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.

Abstract: A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.

Abstract: Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Abstract: A computer-implemented method, system, and apparatus for providing interactive and analytical components that provide a comprehensive and dynamic tool for therapies to prevent and reverse dementia-related diseases. The invention includes one or more computers that receive and store personal information for people. The computers also generate synergic data specifying an expected adjustment of individual biological. For each person, the computers process personal information and identify a subset of biological mechanisms that are principally affected by dementia-related diseases or the substantial risk of dementia-related diseases. The computers also apply the personal generate for each person one or more messages communicating a therapy plan containing a combination of therapies and determines how to apply the therapies. The computers use several means to collect therapy compliance information and convey correctional instructions from coaches.

Abstract: Encryption of data within a memory is provided by key generation circuitry which serves to generate a key as a function of the address within the memory being accessed and then encryption circuitry or decryption circuitry which serve respectively to encrypt or decrypt the data as a function of the key that has been generated based upon the address. The encryption and the decryption may be performed using a bitwise XOR operation. The key generation circuitry may have the form of physically unclonable function circuitry, which varies from instance to instance of implementation and that operates to generate the same key for the same address upon both write and read operations within the same instance.

Abstract: An apparatus has a plurality of storage units. A parity generator is configured to generate a parity value in dependence on the respective values stored in the plurality of storage units. The parity generator is configured such that determination of the parity value is independent of a read access to the data stored the plurality of storage units. A detector is configured to detect a change in value of the parity value.

Abstract: Encryption of data within a memory 6 is provided by key generation circuitry 12 which serves to generate a key as a function of the address within the memory 6 being accessed and then encryption circuitry 14 or decryption circuitry 16 which serve respectively to encrypt or decrypt the data as a function of the key that has been generated based upon the address. The encryption and the decryption may be performed using a bitwise XOR operation. The key generation circuitry may have the form of physically unclonable function circuitry, which varies from instance to instance of implementation and that operates to generate the same key for the same address upon both write and read operations within the same instance.

Abstract: Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.

Abstract: An integrated circuit device has at least one environment-hardened die and at least one less-environment-hardened die. Environment-hardened circuitry on the environment-hardened die is more resistant to the degradation when exposed to a predetermined environmental condition than the less-environment-hardened circuitry on the environment-hardened die. The dice are combined using a 3D or 2.5D integrated circuit technology. This is very useful for testing circuits at adverse environmental conditions (e.g. high temperature), or for providing circuits to operate at such conditions.

Abstract: An electrical component is formed with a directed self assembly portion having a random electrical characteristic, such as resistance or capacitance. The random pattern can be produced by using a directed self assembly polymer with guide structures 2 including randomness inducing features. The electrical components with the random electrical characteristics may be used in electrical circuits relying upon random variation in electrical characteristics, such as physically unclonable function circuitry. The electrical components may be resistors and/or capacitors.

Abstract: Encryption of data within a memory 6 is provided by key generation circuitry 12 which serves to generate a key as a function of the address within the memory 6 being accessed and then encryption circuitry 14 or decryption circuitry 16 which serve respectively to encrypt or decrypt the data as a function of the key that has been generated based upon the address. The encryption and the decryption may be performed using a bitwise XOR operation. The key generation circuitry may have the form of physically unclonable function circuitry, which varies from instance to instance of implementation and that operates to generate the same key for the same address upon both write and read operations within the same instance.

Abstract: A user selection of an item corresponding to a Web page can be received. The user selection can represents a request to open the Web page within an instantiated one of a set of Web browser applications installed on a computing device. A set of Web page elements unique to the Web page can be identified through an analysis conducted by the computing device. The identified set of Web page elements can be utilized to determine at the computing device one of the installed Web browser applications for the Web page. The determination of the one installed Web browser application can varies from Web page-to-Web page. At the computing device, the determined one of the Web browser applications can be instantiated. The Web page can be opened within the instantiated one of the Web browser applications.

Abstract: A data storage apparatus is provided which has a plurality of data storage units, each respective data storage unit configured to store a respective data bit of a data word. Stored data value parity generation circuitry is configured to generate a parity bit for the data word in dependence on the data bits of the data word stored in the plurality of data storage units. The stored data value parity generation circuitry is configured such that switching within the stored data value parity generation circuitry does not occur when the data word is read out from the plurality of data storage units. Transition detection circuitry is configured to detect a change in value of the parity bit.

Abstract: An apparatus has a plurality of storage units. A parity generator is configured to generate a parity value in dependence on the respective values stored in the plurality of storage units. The parity generator is configured such that determination of the parity value is independent of a read access to the data stored the plurality of storage units. A detector is configured to detect a change in value of the parity value.

Abstract: Apparatus for storing data and a method of adapting a duration of a wordline pulse in an apparatus for storing data are provided. Sensor circuitry comprises a calibrated bitcell which is calibrated to use a duration of wordline pulse which matches a longest wordline pulse required by any bitcell in an array of bitcells for a successful write operation to be carried out. The duration of wordline pulse is signalled to wordline pulse circuitry, which generates a wordline pulse for the array of bitcells with this wordline pulse duration. The sensor circuitry is configured to adapt the wordline pulse duration in dependence on current local conditions in which the apparatus operates to compensate for influence of the current local conditions on the longest wordline pulse required by any bitcell in the array of bitcells.

Abstract: Apparatus for storing data and a method of adapting a duration of a wordline pulse in an apparatus for storing data are provided. Sensor circuitry comprises a calibrated bitcell which is calibrated to use a duration of wordline pulse which matches a longest wordline pulse required by any bitcell in an array of bitcells for a successful write operation to be carried out. The duration of wordline pulse is signalled to wordline pulse circuitry, which generates a wordline pulse for the array of bitcells with this wordline pulse duration. The sensor circuitry is configured to adapt the wordline pulse duration in dependence on current local conditions in which the apparatus operates to compensate for influence of the current local conditions on the longest wordline pulse required by any bitcell in the array of bitcells.

Abstract: A storage circuit 2 in the form of a master slave latch includes a slave stage 6 serving as a bit storage circuit. The slave stage 6 includes an inverter chain which when operating in a normal mode includes an even number of inverters 10, 12 and when operating in an random number generation mode includes an odd number of inverters 10, 12, 14 and so functions as a free running ring oscillator. When a switch is made back from the random number generation mode to the normal mode, then the oscillation ceases and a stable pseudo random bit value is output from the bit value storage circuit 6.

Abstract: Inheritance contributions of programming class functions and class variables are diagrammed. A functional diagram illustrates individual class contributions of functions. A variable composition diagram illustrates individual class contributions of variables. A diagrammatic depiction of functions overridden and functions contributed in the inheritance hierarchy is provided. Functions which are unique, overridden and/or have contributions in different classes of the hierarchy are visually distinguished (e.g., by distinguishing marks). Classes in the hierarchy are graphically depicted with relative sizes based on percent contribution.