Abstract: In certain embodiments, resolved exceptions information regarding resolved exceptions may be obtained. The resolved exceptions information may indicate the resolved exceptions and, for each resolved exception of the resolved exceptions, a set of attributes of a transaction for which the resolved exception was triggered. The resolved exceptions information may be provided as input to a prediction model to obtain multiple decision trees via the prediction model. Each decision tree of the multiple decision trees may comprise nodes and conditional branches, each node of the nodes of the decision tree indicating a probability of a dividend-related classification for a transaction that corresponds to the node. A decision tree may be obtained from the multiple decision trees.

Abstract: In one example, a video conferencing method to align video conference participant windows is disclosed. The method determines a position of a camera that captures images of a video conference participant. The method determines which one of multiple participant windows is a speaker participant window and aligns the speaker participant window with the position of the camera. The method may capture user-input parameters of an area adjacent to the camera to position the speaker participant window.

Abstract: In one example, a video conferencing method to align video conference participant windows is disclosed. The method determines a position of a camera that captures images of a video conference participant. The method determines which one of multiple participant windows is a speaker participant window and aligns the speaker participant window with the position of the camera. The method may capture user-input parameters of an area adjacent to the camera to position the speaker participant window.

Abstract: The present disclosure relates to a system and method for electronic design. Embodiments may include receiving, using at least one processor, a plurality of distinct electronic designs at an electronic design database and storing the plurality of distinct electronic designs at the electronic design database. Embodiments may further include receiving a request to reuse one of the plurality of distinct electronic designs from a client electronic device associated with a user, wherein the request includes design connectivity information, block connectivity information, and page connectivity information. Embodiments may also include analyzing the design connectivity information, block connectivity information, and page connectivity information to identify one or more closest matches with the plurality of distinct electronic designs and providing the one or more closest matches to the client electronic device to allow for subsequent displaying at a graphical user interface.

Abstract: In an electronic circuit design system, dynamic visual guidance for relative placement of mutually paired electronic components, such as a bypass capacitance portion and a power pin in a power domain, is provided. A first, selected component is adaptively paired with one of a plurality of second components eligible for pairing with the first component, according to predetermined pairing criteria such as proximity criteria. A mutual placement zone between the paired components is generated to define a locus of valid placement locations of the paired first and second components one with respect to the other according to predetermined placement criteria therefor. Visual indicia to represent the mutual placement zone is generated, thereby providing visual guidance to reposition the first component.

Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. Embodiments may include storing one or more electronic circuit designs at an electronic circuit design database and receiving a user input associated with one of the electronic circuit designs. Embodiments may include scanning the one or more stored electronic circuit designs and generating a network including a relationship graph and a component map, based upon, at least in part, the scanning Embodiments may include generating at least one next neighbor component based upon, at least in part, the network and the received user input. Embodiments may include displaying one or more user-selectable options at a graphical user interface, wherein the user-selectable options include the at least one next neighbor component.

Abstract: A method is provided that includes receiving shape data specifying a shape of an electromagnetic (EM) structure in a circuit layout and transferring the shape data to a schematic cell representation based on a logic function of the EM structure and package technology layers of the circuit layout. The method includes placing a symbol for the EM structure in the schematic cell representation, associating the shape data and a model path with a cell parameter in the symbol, mapping the shape data to the package technology layers, and specifying pins in the schematic cell representation according to the shape data. Further, the method includes verifying ports for the EM structure and placing the EM structure in a package layout for a printed circuit board (PCB). A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.

Abstract: In certain embodiments, resolved exceptions information regarding resolved exceptions may be obtained. The resolved exceptions information may indicate the resolved exceptions and, for each resolved exception of the resolved exceptions, a set of attributes of a transaction for which the resolved exception was triggered. The resolved exceptions information may be provided as input to a prediction model to obtain multiple decision trees via the prediction model. Each decision tree of the multiple decision trees may comprise nodes and conditional branches, each node of the nodes of the decision tree indicating a probability of a dividend-related classification for a transaction that corresponds to the node. A decision tree may be obtained from the multiple decision trees.

Abstract: A method and system are provided for automatically enforcing a schematic layout strategy applied to a group of schematically represented circuit objects of an electronic circuit design. A circuit editing tool electronically renders schematic representations of circuit objects responsive to user input. A layout object acquisition unit coupled to the circuit editing tool actuates responsive to user input to selectively apply a predetermined layout strategy to at least one group of circuit objects for generating a corresponding layout object. The predetermined layout strategy includes a defining set of placement and interconnection routing schemes for the grouped circuit objects, one relative to the other. A layout object management unit coupled to the layout object acquisition unit and circuit editing tool adaptively reconfigures the layout object in accordance with the layout strategy thereof responsive to an editing operation being imposed on at least one circuit object within the layout object.

Abstract: Various embodiments implement multi-fabric designs by using respective EDA tools associated with multiple design fabrics to access their respective native design data. Each EDA tool has access to and processes or manipulates its corresponding native design data; and no EDA tools have the visibility of the entire multi-fabric electronic design. Requests for actions are automatically transmitted among these EDA tools to instantiate desired EDA tools and to descend or ascend the multi-fabric design structure so that native design data in a particular design fabric are processed by the corresponding EDA tool(s) within the context of the other design fabrics. These techniques enable designers to implement, check, verify, simulate, analyze, probe, and netlist the entire electronic design across multiple design fabric.

Abstract: Described are methods and systems for netlisting or probing multi-fabric designs that identify a request for process at least a portion of a multi-fabric electronic design and determine a first partial listing of one or more first circuit components in response to the request by at least identifying first design data in a first design fabric of the one or more first circuit components using a first session of a first electronic design automation (EDA) tool. The methods and systems further automatically transmit a request for action related to the one or more first circuit components from the first session to a second session of a second EDA tool and determine a second partial listing of one or more second circuit components by at least identifying second design data in a second design fabric of the one or more second circuit components using the second session.

Abstract: Disclosed are techniques to analyze multi-fabric designs. These techniques generate a cross-fabric analysis model by at least identifying first design data in a first design fabric of a multi-fabric electronic design using a first session of a first electronic design automation (EDA) tool, update the cross-fabric simulation model by at least identifying second design data in a second design fabric using a second session of a second EDA tool, and determine analysis results for the multi-fabric electronic design using at least the cross-fabric simulation model. Analysis results may be determined using parasitic, electrical, or performance information.

Abstract: Disclosed are various techniques that check, verify, or test multi-fabric designs by receiving a request for checking correctness of a multi-fabric design across at least a first design fabric and a second design fabric. A request for action is transmitted from a first EDA tool session to a second EDA tool session. Connectivity information of second design data in the second design fabric is identified by the second EDA tool session in response to the request for action from the first EDA tool session. These various techniques then check the correctness of the multi-fabric design in the first design fabric by using at least the connectivity information of the second design data. A symbolic representation may be used to represent design data in an EDA tool session to which the design data are not native.

Abstract: The present disclosure relates to a computer-implemented method for visualization in an electronic design. The method may include providing an electronic design and receiving a selection of at least one pin associated with the electronic design at a first graphical user interface. The method may further include generating a stub for each of the selected pins at the first graphical user interface. The method may also include providing a second graphical user interface configured to allow for the assignment of a signal name to each stub. The method may include extending the stub for each of the selected pins to reach a target destination associated with the electronic design. The method may also include displaying the signal name for each stub on at least one of the first graphical user interface and the second graphical user interface.

Abstract: A method and system are provided for maintaining dynamic visual cues/graphic indicia for associated circuitry of a schematic object. The dynamic visual cues or graphic indicia indicate a number of states of the parent circuit object and its associated circuitry. The visibility, placement status, and other attributes of the parent or associated circuitry may be quickly discerned by inspection of the visual indicia. Navigation, including manipulations of one or both of the parent and associated circuitry are available through actuation of the visual cue or a selectable button proximately disposed thereto.

Abstract: A method of connecting an interface to a fabric of an electronic device, the interface having a plurality of nets to be connected to corresponding connectors in the fabric includes associating with each of the connectors in the fabric a first variable indicating that the connector belongs to the interface; associating with each of the connectors in the fabric a second variable indicating a number of higher numbered adjacent connectors for the connector in the interface; connecting each of the nets in the interface to a corresponding one of the connectors in the fabric such that the second variable has a non-zero value at exactly one of the corresponding connectors in the interface.

Abstract: A method of specifying system level constraints for connecting an interface of an electronic device between first and second fabrics includes specifying one or more first condition relating to a placement of the interface, specifying one or more second condition relating to a connection of a net in the interface between the first and second fabrics, generating one or more first equation expressing the first condition as a function of the location of the connectors, generating one or more second equation expressing the second condition as a function of the location of connectors, generating one or more third equation expressing an optimality criterion for the interface, and outputting the one or more first equation, the one or more second equation and the one or more third equation to a data file in a computer readable format.

Abstract: An interface object library tool for manipulating interface objects for a printed circuit board (PCB) tool is disclosed. The interface object library tool includes a hierarchical interface display module, an input module, and a store. The hierarchical interface display module is configured to display an interrelation between a plurality of interface objects and a plurality of groups each including a plurality of signal, power and ground lines. The plurality of interface objects are configured to be associated with a plurality of block objects to define a plurality of component objects. The input module is configured to: accept association of the plurality of groups and the plurality of signal, power and ground lines without defining pin or pad assignments; and accept association between the plurality of interface objects and a plurality of groups.

Abstract: A method of interconnecting a first plurality of electronic components and a second plurality of electronic components to form an electronic circuit includes exporting a first netlist representing a first interconnection of the first electronic components in a first design entry tool, exporting a second netlist representing a second interconnection of the second electronic components in a second design entry tool, providing at least a first interface from the second plurality to the first plurality in the second design entry tool, populating the first interface through the first design entry tool, and exporting a third netlist representing the first interface from the second plurality to the first plurality from the second design entry tool, wherein the third netlist stitches the first netlist to the second netlist.

Abstract: A system for connecting an interface of an electronic device between first and second fabrics includes a constraint generator that associates first and second conditions with the interface, a first equation solver that solves one or more first equation to select a first plurality of connectors in the first fabric and a second plurality of connectors in the second fabric that satisfy the first condition based on an optimality criterion for the interface; and a second equation solver that solves one or more second equation to select one of the first plurality of connectors in the fabric and one of the second plurality of connectors in the second fabric that satisfy the second condition based on the optimality criterion for the interface.