Patents by Inventor Vikas Kohli

Vikas Kohli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8271933
    Abstract: A printed circuit board (PCB) block diagram tool for block diagram level editing of a PCB design abstracted from a PCB physical layout tool is disclosed. The PCB block diagram tool includes a plurality of interface objects, a plurality of block objects and interconnect lines. The plurality of interface objects represents interfaces between components. Each of the plurality of interface objects include a plurality of signal, power and ground signal lines without defined physical assignment to pin or pad. The plurality of block objects represents a plurality of physical objects in the PCB physical layout tool. The plurality of blocks are configured to accept the plurality of interface objects. Interconnect lines connect the plurality of interface objects between the plurality of block objects.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: September 18, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vikas Kohli, Dhamarajan Sankaran, Steve R. Durrill
  • Patent number: 7990375
    Abstract: Embodiments of the present invention provide a virtual-view schematic editor for use in CAD systems. In response to a user request, the editor selects elements from a CAD database, determines the connectivity between the elements, and renders the elements on a single display. Virtual views may be created and stored for later re-use within the system.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: August 2, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vikas Kohli, Parag Choudhary
  • Publication number: 20110153289
    Abstract: A method of specifying system level constraints for connecting an interface of an electronic device between first and second fabrics includes specifying one or more first condition relating to a placement of the interface, specifying one or more second condition relating to a connection of a net in the interface between the first and second fabrics, generating one or more first equation expressing the first condition as a function of the location of the connectors, generating one or more second equation expressing the second condition as a function of the location of connectors, generating one or more third equation expressing an optimality criterion for the interface, and outputting the one or more first equation, the one or more second equation and the one or more third equation to a data file in a computer readable format.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Utpal BHATTACHARYA, Vikas KOHLI, Tarun BERI, Rahul VERMA
  • Publication number: 20110153288
    Abstract: A method of connecting an interface to a fabric of an electronic device, the interface having a plurality of nets to be connected to corresponding connectors in the fabric includes associating with each of the connectors in the fabric a first variable indicating that the connector belongs to the interface; associating with each of the connectors in the fabric a second variable indicating a number of higher numbered adjacent connectors for the connector in the interface; connecting each of the nets in the interface to a corresponding one of the connectors in the fabric such that the second variable has a non-zero value at exactly one of the corresponding connectors in the interface.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Utpal BHATTACHARYA, Vikas KOHLI, Tarun BERI, Rahul VERMA
  • Publication number: 20110154276
    Abstract: A system for connecting an interface of an electronic device between first and second fabrics includes a constraint generator that associates first and second conditions with the interface, a first equation solver that solves one or more first equation to select a first plurality of connectors in the first fabric and a second plurality of connectors in the second fabric that satisfy the first condition based on an optimality criterion for the interface; and a second equation solver that solves one or more second equation to select one of the first plurality of connectors in the fabric and one of the second plurality of connectors in the second fabric that satisfy the second condition based on the optimality criterion for the interface.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Utpal BHATTACHARYA, Vikas KOHLI, Tarun BERI, Rahul VERMA
  • Publication number: 20070229537
    Abstract: Embodiments of the present invention provide a virtual-view schematic editor for use in CAD systems. In response to a user request, the editor selects elements from a CAD database, determines the connectivity between the elements, and renders the elements on a single display. Virtual views may be created and stored for later re-use within the system.
    Type: Application
    Filed: April 3, 2006
    Publication date: October 4, 2007
    Applicant: Cadence Design Systems, Inc.
    Inventors: Vikas Kohli, Parag Choudhary
  • Patent number: 7168041
    Abstract: Views for signals and instances are provided in a table based design entry system. The signal view allows a designer to enter signals to be used in a design. The signals may be individually entered or imported from pre-defined or external packages of signals. The instance view allows the designer to enter components and to define connectivity of pins of the components to signals. The components may be entered individually or imported from predefined or external packages. An naming routines provides signal name generation and copying names of other components (e.g., pin names) to name the signals. Data entered into the table based entry system is checked for errors (duplicate names, syntax, etc.), and exported to other design tools for processes such as simulation, layout, etc.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: January 23, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steve Durrill, Vikas Kohli
  • Patent number: 7143341
    Abstract: Concurrent engineering among multiple design groups is facilitated by maintaining design changes in a data model of a design being developed. Design changes for each group are made from a baseline design. Changes are tracked by maintaining change information from all but an owner of the original baseline design. Changes are synchronized by identifying owner and non-owner changes and merging the changes to produce a final design. Since non-owner changes are tracked, the baseline design is not needed in synchronization. Preferably the invention is applied to electronic designs made by multiple design groups at geographically diverse locations. The invention may also be applied to any system where configuration management of developed software, parts, or any design is needed.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: November 28, 2006
    Assignee: Cadence Design Systems
    Inventor: Vikas Kohli