Patents by Inventor Vinay Prabhakar
Vinay Prabhakar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180046088Abstract: Implementations described herein generally relate to methods for leveling a component above a substrate. In one implementation, a test substrate is placed on a substrate support inside of a processing chamber. A component, such as a mask, is located above the substrate. The component is lowered to a position so that the component and the substrate are in contact. The component is then lifted and the particle distribution on the test substrate is reviewed. Based on the particle distribution, the component may be adjusted. A new test substrate is placed on the substrate support inside of the processing chamber, and the component is lowered to a position so that the component and the new test substrate are in contact. The particle distribution on the new test substrate is reviewed. The process may be repeated until a uniform particle distribution is shown on a test substrate.Type: ApplicationFiled: August 11, 2017Publication date: February 15, 2018Inventors: Hiroyuki OGISO, Jianhua ZHOU, Zonghui SU, Juan Carlos ROCHA-ALVAREZ, Jeongmin LEE, Karthik Thimmavajjula NARASIMHA, Rick GILBERT, Sang Heon PARK, Abdul Aziz KHAJA, Vinay PRABHAKAR
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Patent number: 9875922Abstract: A system for processing substrates has a vacuum enclosure and a processing chamber situated to process wafers in a processing zone inside the vacuum enclosure. Two rail assemblies are provided, one on each side of the processing zone. Two chuck arrays ride, each on one of the rail assemblies, such that each is cantilevered on one rail assemblies and support a plurality of chucks. The rail assemblies are coupled to an elevation mechanism that places the rails in upper position for processing and at lower position for returning the chuck assemblies for loading new wafers. A pickup head assembly loads wafers from a conveyor onto the chuck assemblies. The pickup head has plurality of electrostatic chucks that pick up the wafers from the front side of the wafers. Cooling channels in the processing chucks are used to create air cushion to assist in aligning the wafers when delivered by the pickup head.Type: GrantFiled: April 14, 2016Date of Patent: January 23, 2018Assignee: INTEVAC, INC.Inventors: Terry Pederson, Henry Hieslmair, Moon Chun, Vinay Prabhakar, Babak Adibi, Terry Bluck
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Publication number: 20170236740Abstract: A chuck for wafer processing that counters the deleterious effects of thermal expansion of the wafer. Also, a combination of chuck and shadow mask arrangement that maintains relative alignment between openings in the mask and the wafer in spite of thermal expansion of the wafer. A method for fabricating a solar cell by ion implant, while maintaining relative alignment of the implanted features during thermal expansion of the wafer.Type: ApplicationFiled: January 19, 2017Publication date: August 17, 2017Inventors: Terry Bluck, Babak Adibi, Vinay Prabhakar, William Eugene Runstadler, JR.
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Patent number: 9583661Abstract: A grid for minimizing effects of ion divergence in plasma ion implant. The plasma grid is made of a flat plate having a plurality of holes, wherein the holes are arranged in a plurality of rows and a plurality of columns thereby forming beamlets of ions that diverge in one direction. A mask is used to form the implanted shapes on the wafer, wherein the holes in the mask are oriented orthogonally to the direction of beamlet divergence.Type: GrantFiled: March 17, 2016Date of Patent: February 28, 2017Assignee: INTEVAC, INC.Inventors: Vinay Prabhakar, Babak Adibi
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Patent number: 9543114Abstract: System and method to align a substrate under a shadow mask. A substrate holder has alignment mechanism, such as rollers, that is made to abut against an alignment straight edge. The substrate is then aligned with respect to the straight edge and is chucked to the substrate holder. The substrate holder is then transported into a vacuum processing chamber, wherein it is made to abut against a mask straight edge to which the shadow mask is attached and aligned to. Since the substrate was aligned to an alignment straight edge, and since the mask is aligned to the mask straight edge that is precisely aligned to the alignment straight edge, the substrate is perfectly aligned to the mask.Type: GrantFiled: August 5, 2015Date of Patent: January 10, 2017Assignee: INTEVAC, INC.Inventors: Babak Adibi, Vinay Prabhakar, Terry Bluck
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Publication number: 20160233122Abstract: A system for processing substrates has a vacuum enclosure and a processing chamber situated to process wafers in a processing zone inside the vacuum enclosure. Two rail assemblies are provided, one on each side of the processing zone. Two chuck arrays ride, each on one of the rail assemblies, such that each is cantilevered on one rail assemblies and support a plurality of chucks. The rail assemblies are coupled to an elevation mechanism that places the rails in upper position for processing and at lower position for returning the chuck assemblies for loading new wafers. A pickup head assembly loads wafers from a conveyor onto the chuck assemblies. The pickup head has plurality of electrostatic chucks that pick up the wafers from the front side of the wafers. Cooling channels in the processing chucks are used to create air cushion to assist in aligning the wafers when delivered by the pickup head.Type: ApplicationFiled: April 14, 2016Publication date: August 11, 2016Inventors: Terry Pederson, Henry Hieslmair, Moon Chun, Vinay Prabhakar, Babak Adibi, Terry Bluck
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Publication number: 20160204295Abstract: A grid for minimizing effects of ion divergence in plasma ion implant. The plasma grid is made of a flat plate having a plurality of holes, wherein the holes are arranged in a plurality of rows and a plurality of columns thereby forming beamlets of ions that diverge in one direction. A mask is used to form the implanted shapes on the wafer, wherein the holes in the mask are oriented orthogonally to the direction of beamlet divergence.Type: ApplicationFiled: March 17, 2016Publication date: July 14, 2016Inventors: Vinay Prabhakar, Babak Adibi
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Patent number: 9324598Abstract: A system for processing substrates has a vacuum enclosure and a processing chamber situated to process wafers in a processing zone inside the vacuum enclosure. Two rail assemblies are provided, one on each side of the processing zone. Two chuck arrays ride, each on one of the rail assemblies, such that each is cantilevered on one rail assemblies and support a plurality of chucks. The rail assemblies are coupled to an elevation mechanism that places the rails in upper position for processing and at lower position for returning the chuck assemblies for loading new wafers. A pickup head assembly loads wafers from a conveyor onto the chuck assemblies. The pickup head has plurality of electrostatic chucks that pick up the wafers from the front side of the wafers. Cooling channels in the processing chucks are used to create air cushion to assist in aligning the wafers when delivered by the pickup head.Type: GrantFiled: November 8, 2012Date of Patent: April 26, 2016Assignee: INTEVAC, INC.Inventors: Terry Pederson, Henry Hieslmair, Moon Chun, Vinay Prabhakar, Babak Adibi, Terry Bluck
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Patent number: 9318332Abstract: A grid for minimizing effects of ion divergence in plasma ion implant. The plasma grid is made of a flat plate having a plurality of holes, wherein the holes are arranged in a plurality of rows and a plurality of columns thereby forming beamlets of ions that diverge in one direction. A mask is used to form the implanted shapes on the wafer, wherein the holes in the mask are oriented orthogonally to the direction of beamlet divergence.Type: GrantFiled: December 19, 2013Date of Patent: April 19, 2016Assignee: INTEVAC, INC.Inventors: Vinay Prabhakar, Babak Adibi
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Publication number: 20160042913Abstract: System and method to align a substrate under a shadow mask. A substrate holder has alignment mechanism, such as rollers, that is made to abut against an alignment straight edge. The substrate is then aligned with respect to the straight edge and is chucked to the substrate holder. The substrate holder is then transported into a vacuum processing chamber, wherein it is made to abut against a mask straight edge to which the shadow mask is attached and aligned to. Since the substrate was aligned to an alignment straight edge, and since the mask is aligned to the mask straight edge that is precisely aligned to the alignment straight edge, the substrate is perfectly aligned to the mask.Type: ApplicationFiled: August 5, 2015Publication date: February 11, 2016Inventors: Babak Adibi, Vinay Prabhakar, Terry Bluck
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Publication number: 20140170795Abstract: A grid for minimizing effects of ion divergence in plasma ion implant. The plasma grid is made of a flat plate having a plurality of holes, wherein the holes are arranged in a plurality of rows and a plurality of columns thereby forming beamlets of ions that diverge in one direction. A mask is used to form the implanted shapes on the wafer, wherein the holes in the mask are oriented orthogonally to the direction of beamlet divergence.Type: ApplicationFiled: December 19, 2013Publication date: June 19, 2014Applicant: Intevac, Inc.Inventors: Vinay Prabhakar, Babak Adibi
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Publication number: 20120181170Abstract: Methods, apparatuses, and various apparatus components, such as base plates, lipseals, and contact ring assemblies are provided for reducing contamination of the contact area in the apparatuses. Contamination may happen during removal of semiconductor wafers from apparatuses after the electroplating process. In certain embodiments, a base plate with a hydrophobic coating, such as polyamide-imide (PAI) and sometimes polytetrafluoroethylene (PTFE), are used. Further, contact tips of the contact ring assembly may be positioned further away from the sealing lip of the lipseal. In certain embodiments, a portion of the contact ring assembly and/or the lipseal also include hydrophobic coatings.Type: ApplicationFiled: March 28, 2012Publication date: July 19, 2012Inventors: Vinay Prabhakar, Bryan L. Buckalew, Kousik Ganesan, Shantinath Ghongadi, Zhian He, Steven T. Mayer, Robert Rash, Jonathan D. Reid, Yuichi Takada, James R. Zibrida
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Patent number: 8172992Abstract: Methods, apparatuses, and various apparatus components, such as base plates, lipseals, and contact ring assemblies are provided for reducing contamination of the contact area in the apparatuses. Contamination may happen during removal of semiconductor wafers from apparatuses after the electroplating process. In certain embodiments, a base plate with a hydrophobic coating, such as polyamide-imide (PAI) and sometimes polytetrafluoroethylene (PTFE), are used. Further, contact tips of the contact ring assembly may be positioned further away from the sealing lip of the lipseal. In certain embodiments, a portion of the contact ring assembly and/or the lipseal also include hydrophobic coatings.Type: GrantFiled: December 8, 2009Date of Patent: May 8, 2012Assignee: Novellus Systems, Inc.Inventors: Vinay Prabhakar, Bryan L. Buckalew, Kousik Ganesan, Shantinath Ghongadi, Zhian He, Steven T. Mayer, Robert Rash, Jonathan D. Reid, Yuichi Takada, James R. Zibrida
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Publication number: 20100155254Abstract: Methods, apparatuses, and various apparatus components, such as base plates, lipseals, and contact ring assemblies are provided for reducing contamination of the contact area in the apparatuses. Contamination may happen during removal of semiconductor wafers from apparatuses after the electroplating process. In certain embodiments, a base plate with a hydrophobic coating, such as polyamide-imide (PAI) and sometimes polytetrafluoroethylene (PTFE), are used. Further, contact tips of the contact ring assembly may be positioned further away from the sealing lip of the lipseal. In certain embodiments, a portion of the contact ring assembly and/or the lipseal also include hydrophobic coatings.Type: ApplicationFiled: December 8, 2009Publication date: June 24, 2010Inventors: Vinay Prabhakar, Bryan L. Buckalew, Kousik Ganesan, Shantinath Ghongadi, Zhian He, Steven T. Mayer, Robert Rash, Jonathan D. Reid, Yuichi Takada, James R. Zibrida