Abstract: An example operation may include one or more of receiving a structured query language (SQL) request which applies to a subset of blocks from among blocks stored on a blockchain ledger, storing, in a cache, a portion of the blocks from among the blocks stored on the blockchain ledger, identifying one or more blocks which the SQL request applies to, which are not stored in the cache, and retrieving the identified one or more blocks not stored in the cache from the blockchain ledger, performing an SQL operation to merge one or more blocks from the cache which the SQL request applies to and the one or more blocks retrieved from the blockchain ledger, and transmitting the merged blocks to a computing system that is associated with the received SQL request.

Abstract: An example operation may include one or more of receiving a structured query language (SQL) request which applies to a subset of blocks from among blocks stored on a blockchain ledger, storing, in a cache, a portion of the blocks from among the blocks stored on the blockchain ledger, identifying one or more blocks which the SQL request applies to, which are not stored in the cache, and retrieving the identified one or more blocks not stored in the cache from the blockchain ledger, performing an SQL operation to merge one or more blocks from the cache which the SQL request applies to and the one or more blocks retrieved from the blockchain ledger, and transmitting the merged blocks to a computing system that is associated with the received SQL request.

Abstract: Hardware architectures for ultrasonic front-end receivers used in ultrasonic sensing applications are disclosed. An example ultrasonic receiver may include a plurality of ultrasonic sensor elements. A given ultrasonic sensor element may be configured to detect an ultrasonic signal/wave that has interacted with an object being analyzed, such as a finger, if determining a fingerprint is the target of the ultrasonic sensing. The ultrasonic sensor element is further configured to generate an electrical signal indicative of the ultrasonic signal that has been detected. In contrast to conventional implementations, the electrical signal is integrated in an analog domain, prior to being converted to digital domain for further processing. Various embodiments of the ultrasonic receivers disclosed herein may benefit from one or more of reduced power consumption, reduced die area requirements, and reduced cost due to the use of a more efficient architecture.

Abstract: Various transimpedance amplifier (TIA) arrangements for ultrasonic front-end receivers used in ultrasonic sensing applications are disclosed. An example TIA includes three common-source gain stages in a feedback loop with a common-gate stage. In some aspects, the TIA may include a level shifter configured to maintain the voltage at the gate of a transistor used to implement the first common-source gain stage of the feedback loop shifted by a certain amount with respect to the voltage at an input port to the TIA. In some aspects, at least portions of the TIA may be biased using bias currents that are configured to be process-, supply voltage-, and/or temperature-dependent. Various embodiments of the TIAs disclosed herein may benefit from one or more of the following advantages: reduced noise, reduced input impedance, reduced temperature coefficient of input impedance, and stability for a wide range of sensor frequencies.

Abstract: Various transimpedance amplifier (TIA) arrangements for ultrasonic front-end receivers used in ultrasonic sensing applications are disclosed. An example TIA includes three common-source gain stages in a feedback loop with a common-gate stage. In some aspects, the TIA may include a level shifter configured to maintain the voltage at the gate of a transistor used to implement the first common-source gain stage of the feedback loop shifted by a certain amount with respect to the voltage at an input port to the TIA. In some aspects, at least portions of the TIA may be biased using bias currents that are configured to be process-, supply voltage-, and/or temperature-dependent. Various embodiments of the TIAs disclosed herein may benefit from one or more of the following advantages: reduced noise, reduced input impedance, reduced temperature coefficient of input impedance, and stability for a wide range of sensor frequencies.

Abstract: Embodiments of the invention are generally directed driving data of multiple protocols through a single set of pins. An embodiment of an apparatus includes a transmitter connected to two pads on an IC the transmitter including a differential driver to transmit a differential signal, wherein the differential driver has a first branch and a second branch, each branch of the differential driver including a protection device connected to one of the pads; and a common mode driver to transmit a common mode signal, the common mode driver having a first branch and a second branch, each of the branches of the common mode driver including a protection device connected to one of the pads. The first and second switch devices are not turned on simultaneously, based on data to be transmitted, one of the switch devices being turned on and the other being turned off.

Abstract: Aspects of the embodiments are directed an analog front end circuit (AFE circuit), the AFE circuit including a beamforming circuit configured to receive as an input a plurality of receiver inputs, the receiver inputs coupled to a sensor element. The beamforming circuit can include a plurality of receiver sub-circuits, each sub-circuit including a digital-to-analog converter, a low noise amplifier, and an I/Q mixer circuit element; an adder circuit element at an output of the I/Q mixer circuit element; and a multiplexer coupled to an output of the adder circuit. The AFE can be part of a current sensing device. The current sensing device can include a two-dimensional array of sensor elements.

Abstract: Embodiments of the invention are generally directed driving data of multiple protocols through a single set of pins. An embodiment of an apparatus includes a transmitter connected to two pads on an IC the transmitter including a differential driver to transmit a differential signal, wherein the differential driver has a first branch and a second branch, each branch of the differential driver including a protection device connected to one of the pads; and a common mode driver to transmit a common mode signal, the common mode driver having a first branch and a second branch, each of the branches of the common mode driver including a protection device connected to one of the pads. The first and second switch devices are not turned on simultaneously, based on data to be transmitted, one of the switch devices being turned on and the other being turned off.

Abstract: Embodiments of the invention are generally directed to elements to counter transmitter circuit performance limitations. An embodiment of an apparatus for driving data on a differential channel including a first output terminal and a second output terminal includes a differential driver circuit; and a first pre-driver and a second pre-driver, where each pre-driver has an output, wherein the first output terminal of the apparatus is coupled to the output of the first pre-driver, and the second output terminal of the apparatus is coupled to the output of the second pre-driver, where each pre-driver includes one or more capacitors, a first end of each capacitor being connected to the output of the pre-driver and a second end of each of the capacitors being connected to a sub-pre-driver circuit.

Abstract: Embodiments of the invention are generally directed driving data of multiple protocols through a single set of pins. An embodiment of an apparatus includes a transmitter connected to two pads on an IC the transmitter including a differential driver to transmit a differential signal, wherein the differential driver has a first branch and a second branch, each branch of the differential driver including a protection device connected to one of the pads; and a common mode driver to transmit a common mode signal, the common mode driver having a first branch and a second branch, each of the branches of the common mode driver including a protection device connected to one of the pads. The first and second switch devices are not turned on simultaneously, based on data to be transmitted, one of the switch devices being turned on and the other being turned off.

Abstract: Techniques and mechanisms for switching between a plurality of inputs each to receive a respective analog signal to be transmitted. In an embodiment, switch circuitry comprises a first input to receive a first signal, a second input to receive a second signal, and one or more T-coil circuits including a first T-coil circuit. A first configuration of the switch circuitry includes a first signal path via a first switch coupled between the first input and a primary input node of the first T-coil circuit. A second configuration of the switch circuitry includes a second signal path via a second switch coupled between the second input and a secondary input node of the first T-coil circuit. In an embodiment, control logic transitions the switch circuitry among a plurality of configurations including the first configuration and the second configuration.

Abstract: Techniques and methods for performing asymmetric, full-duplex communication via a signal line. In an embodiment, a transceiver includes transmit circuitry to transmit a first signal via a node coupled to a signal line, where the first signal is transmitted concurrently with the transceiver receiving a second signal via the node at a substantially different data rate than that of the first signal. In another embodiment, signal processing circuitry of the transceiver detects a composite signal at the node, the composite signal including a combination of the first signal and the second signal. Based on the combination of the first signal and the second signal, the signal processing circuitry generates a processed signal, including the signal processing circuitry reducing a contribution by the first signal. The processed signal is provided to receiver circuitry of the transceiver.

Abstract: Embodiments of the invention are generally directed driving data of multiple protocols through a single set of pins. An embodiment of an apparatus includes a transmitter connected to two pads on an IC the transmitter including a differential driver to transmit a differential signal, wherein the differential driver has a first branch and a second branch, each branch of the differential driver including a protection device connected to one of the pads; and a common mode driver to transmit a common mode signal, the common mode driver having a first branch and a second branch, each of the branches of the common mode driver including a protection device connected to one of the pads. The first and second switch devices are not turned on simultaneously, based on data to be transmitted, one of the switch devices being turned on and the other being turned off.

Abstract: Embodiments of the invention are generally directed to elements to counter transmitter circuit performance limitations. An embodiment of an apparatus for driving data on a differential channel including a first output terminal and a second output terminal includes a differential driver circuit; and a first pre-driver and a second pre-driver, where each pre-driver has an output, wherein the first output terminal of the apparatus is coupled to the output of the first pre-driver, and the second output terminal of the apparatus is coupled to the output of the second pre-driver, where each pre-driver includes one or more capacitors, a first end of each capacitor being connected to the output of the pre-driver and a second end of each of the capacitors being connected to a sub-pre-driver circuit.

Abstract: Embodiments of the invention are generally directed to elements to counter transmitter circuit performance limitations. An embodiment of an apparatus for driving data on a differential channel including a first output terminal and a second output terminal includes a differential driver circuit; and a first pre-driver and a second pre-driver, where each pre-driver has an output, wherein the first output terminal of the apparatus is coupled to the output of the first pre-driver, and the second output terminal of the apparatus is coupled to the output of the second pre-driver, where each pre-driver includes one or more capacitors, a first end of each capacitor being connected to the output of the pre-driver and a second end of each of the capacitors being connected to a sub-pre-driver circuit.

Abstract: Techniques and mechanisms for switching between a plurality of inputs each to receive a respective analog signal to be transmitted. In an embodiment, switch circuitry comprises a first input to receive a first signal, a second input to receive a second signal, and one or more T-coil circuits including a first T-coil circuit. A first configuration of the switch circuitry includes a first signal path via a first switch coupled between the first input and a primary input node of the first T-coil circuit. A second configuration of the switch circuitry includes a second signal path via a second switch coupled between the second input and a secondary input node of the first T-coil circuit. In an embodiment, control logic transitions the switch circuitry among a plurality of configurations including the first configuration and the second configuration.

Abstract: Techniques and methods for performing asymmetric, full-duplex communication via a signal line. In an embodiment, a transceiver includes transmit circuitry to transmit a first signal via a node coupled to a signal line, where the first signal is transmitted concurrently with the transceiver receiving a second signal via the node at a substantially different data rate than that of the first signal. In another embodiment, signal processing circuitry of the transceiver detects a composite signal at the node, the composite signal including a combination of the first signal and the second signal. Based on the combination of the first signal and the second signal, the signal processing circuitry generates a processed signal, including the signal processing circuitry reducing a contribution by the first signal. The processed signal is provided to receiver circuitry of the transceiver.

Abstract: Embodiments of the invention are generally directed to elements to counter transmitter circuit performance limitations. An embodiment of an apparatus for driving data on a differential channel including a first output terminal and a second output terminal includes a differential driver circuit; and a first pre-driver and a second pre-driver, where each pre-driver has an output, wherein the first output terminal of the apparatus is coupled to the output of the first pre-driver, and the second output terminal of the apparatus is coupled to the output of the second pre-driver, where each pre-driver includes one or more capacitors, a first end of each capacitor being connected to the output of the pre-driver and a second end of each of the capacitors being connected to a sub-pre-driver circuit.

Abstract: An input buffer for CMOS integrated circuits using sub-micron CMOS technology is affected by the presence of high voltage between various ports of a device. An improvement for such a buffer provides an input voltage limiting circuit making the device mode tolerant to high voltages while using low voltage tolerant CMOS devices. This improvement also reduces the switching level uncertainty due to manufacturing process variations by adding compensation devices to a first inverter stage in the input buffering stage so as to increase noise margin. A hysteresis characteristic is produced by the circuit thus reducing the effect of manufacturing process variation. The circuit can be easily interfaced to other blocks and safely operates in conjunction with relatively high voltage CMOS technology circuitry while achieving the high-speed advantage of thin gate oxide. Low power consumption is achieved by avoiding the possibility of DC current flow in the circuitry.

Abstract: The present invention provides an improved form of inverter circuit which refines the known conventional circuit to reduce its offset and then uses a combination of this refined circuit and a feedback type power converter to achieve low output offset, very high speed and very high current efficiency. According to a first aspect of the present invention there is provided a voltage converter circuit comprising serially coupled first and second gain stages and switching means arranged between the second gain stage and an output for the converter circuit, the first gain stage having a gain greater than that of the second gain stage, and the second gain stage having a bandwidth greater than that of the first gain stage.