Abstract: A display processor device is for processing display image data by overlaying a multitude of image layers. Pixel values of at least one of the image layers are stored in a memory and may comprise pixels values having a single predefined value, such as transparency. The display processor has a fetch unit for selectively fetching stored pixel values from the memory by skipping stored pixels values having the single predefined value according to a fetch mask indicative of pixels values having the single predetermined value. Advantageously the bandwidth for accessing the memory is reduced, because less pixel data values need be retrieved. Power consumption may be reduced, and slower memories may be applied.

Abstract: An audio unit, connected or connectable to a safety-critical apparatus, or integrated or integrable in the apparatus, is proposed. The audio unit may comprise a driver unit, a detection unit, and an alert unit. The driver unit may generate an analog audio signal in response to a request from the apparatus, to drive an acoustic output unit and thereby generate an acoustic signal for a user of the apparatus. The detection unit may detect the audio signal. The alert unit may generate an alert signal in response to the request if the detection unit has not detected the audio signal. It can thus be checked whether the acoustic signal is generated. A method for generating a safety critical acoustic signal is also described.

Abstract: A display controller comprising a blending stage and a blending controller. The blending stage is provided for blending multiple image layers into one display output image and comprises a plurality of input channels for receiving pixel data for the multiple image layers. The blending stage further comprises multiple blenders for combining the pixel data received by at least two input channels of the plurality of input channels. The blending controller is coupled to the blending stage for controlling operation of the blending stage. The blending stage further comprises a controllable switch for coupling an output of at least one blender of the multiple blenders to a display output of the blending stage for regular on-the-fly blending or to an offline blending memory for storing a result of an offline blending task.

Abstract: A memory access controller for managing data flow between a memory unit and a processing unit is described. The memory access controller comprises an addressing unit and an unpacking unit. The addressing unit may receive an address from said processing unit and select a data location within said memory unit in dependence on that address. The unpacking unit may read a first word from the selected data location, unpack the first word into a second word by applying a data conversion scheme which depends on the received address, and provide the second word to the processing unit. The data conversion scheme may comprise, for at least one possible address, a pixel format conversion. A data processing system and a method are also proposed.

Abstract: A data processing system comprising at least a memory unit, a first client connected to the memory unit, and a second client connected to the memory unit is proposed. The first client may comprise a first memory access unit and an information unit. The first memory access unit may read data from or write data to the memory unit at a first data rate. The information unit may update internal data correlating with a minimum required value of the first data rate. The second client may comprise a second memory access unit and a data rate limiting unit. The second memory access unit may read data from or write data to the memory unit at a second data rate. The data rate limiting unit may limit the second data rate in dependence on the internal data. The first memory access unit may, for example, read data packets sequentially from the memory unit, and the information unit may update the internal data at least per data packet. A method of controlling access to a shared memory unit is also proposed.

Abstract: A memory device comprising a memory controller and a homogeneous memory accessible by the memory controller, wherein the homogeneous memory is divided by the memory controller in a first memory partition and a second memory partition, wherein the first memory partition is allocated to a first type of information comprising user data and ECC data that are arranged interleaved with the user data, and wherein the second memory partition is allocated to a second type of information comprising further user data.