Patents by Inventor Vincent Leung

Vincent Leung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8544165
    Abstract: A method of aligning electronic components comprising providing a positioning member 110 having at least one formation 120 for receiving an electronic component; said at least one formation having lateral boundaries 35, 36 for constraining movement of an electronic component; placing a first electronic component 10a in said at least one formation; and providing a force for actively aligning said first electronic component with a lateral boundary of said at least one formation. The force may, for example, be provided by tilting the positioning member, by providing suction or by using an actuator. An apparatus for aligning electronic components and a 3D system of stacked electronic components is also disclosed.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: October 1, 2013
    Assignee: Hong Kong Applied Science & Technology Research Institute Co., Ltd.
    Inventors: Chi Kuen Vincent Leung, Bin Xie, Xunqing Shi
  • Patent number: 8194411
    Abstract: One aspect of the present invention provides an electronic package, comprising at least a first module and a second module arranged on top of the first module, the modules together in the form of a module stack, wherein the first and second modules are adhesively connected together, each module includes a substrate layer having at least one metal layer, at least one die and a plastic(s) package molding compound layer molded over said die or dice, in each module the die or dice are bonded on said substrate layer via the metal layer, a plurality of channels formed generally vertically acting as vias to connect the metal layers and arranged adjacent to the die or dice in at least one of the modules, some or all the channels provided with an inner surface coated with a conductive material layer or filled with a conductive material for electrical connection whereby the dice are electrically connected together, and means serving as an intermediary for providing electrical, mechanical and thermal connectivity, commu
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: June 5, 2012
    Assignee: Hong Kong Applied Science and Technology Research Institute Co. Ltd
    Inventors: Chi Kuen Vincent Leung, Peng Sun, Xunqing Shi, Chang Hwa Tom Chung
  • Publication number: 20110300914
    Abstract: Although the duplexer in a full-duplex transceiver circuit may only be guaranteed by the duplexer manufacturer to have a transmit band rejection from its TX port to its RX port of a certain amount, and may only be guaranteed to have a receive band rejection of another amount, the actual transmit band rejection and the actual receive band rejection of a particular instance of the duplexer may be better than specified. Rather than consuming excess power in the receiver and/or transmitter in order to meet performance requirements assuming the duplexer only performs as well as specified, the duplexer's in-circuit performance is measured as part of a transmitter-to-receiver isolation determination. Transmitter and/or receiver power settings are reduced where possible to take advantage of the measured better-than-specified in-circuit duplexer performance, while still meeting transceiver performance requirements. Power settings are not changed during normal transmit and receive mode operation.
    Type: Application
    Filed: June 4, 2010
    Publication date: December 8, 2011
    Applicant: QUALCOMM INCORPORATED
    Inventors: Prasad S. Gudem, Bhushan Asuri, Soon-Seng Lau, Wingching Vincent Leung
  • Patent number: 8030208
    Abstract: There is described a bonding method for through-silicon-via bonding of a wafer stack in which the wafers are formed with through-silicon-vias and lateral microchannels that are filled with solder. To fill the vias and channels the wafer stack is placed in a soldering chamber and molten solder is drawn through the vias and channels by vacuum. The wafers are held together by layers of adhesive during the assembly of the wafer stack. Means are provided for local reheating of the solder after it has cooled to soften the solder to enable it to be removed from the soldering chamber.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: October 4, 2011
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Chi Kuen Vincent Leung, Peng Sun, Xunqing Shi, Chang Hwa Chung
  • Publication number: 20110235299
    Abstract: A method of aligning electronic components comprising providing a positioning member 110 having at least one formation 120 for receiving an electronic component; said at least one formation having lateral boundaries 35, 36 for constraining movement of an electronic component; placing a first electronic component 10a in said at least one formation; and providing a force for actively aligning said first electronic component with a lateral boundary of said at least one formation. The force may, for example, be provided by tilting the positioning member, by providing suction or by using an actuator. An apparatus for aligning electronic components and a 3D system of stacked electronic components is also disclosed.
    Type: Application
    Filed: March 29, 2010
    Publication date: September 29, 2011
    Inventors: Chi Kuen Vincent Leung, Bin Xie, Xunqing Shi
  • Publication number: 20110230145
    Abstract: In one embodiment, a method includes detecting a power level of a power amplifier coupled to a transceiver during a current burst of a radio communication and providing the detected power level from the power amplifier to the transceiver and controlling a power level of the power amplifier during a next burst based on the detected power level of the current burst.
    Type: Application
    Filed: May 27, 2011
    Publication date: September 22, 2011
    Inventors: Lysander Lim, David Pehlke, John Khoury, Vincent Leung
  • Patent number: 7974596
    Abstract: In one embodiment, a method includes detecting a power level of a power amplifier coupled to a transceiver during a current burst of a radio communication and providing the detected power level from the power amplifier to the transceiver and controlling a power level of the power amplifier during a next burst based on the detected power level of the current burst.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: July 5, 2011
    Assignee: Silicon Laboratories Inc.
    Inventors: Lysander Lim, David Pehlke, John Khoury, Vincent Leung
  • Publication number: 20110147908
    Abstract: The module comprises a first substrate and at least one chip mounted on the first substrate. A second substrate is mounted to the first substrate and has an opening therein. The opening is lined with the at least one chip. The second substrate is overmolded and the first substrate is electrically connected to the second substrate by at least one first electrical connector. At least one second electrical connector extends from the second substrate through the overmold and has its exposed ends for electrical connection to an external module. The external module may be mounted to the first module in order to form a package on package assembly.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Inventors: Peng Sun, Chi Kuen Vincent Leung, Xun Qing Shi
  • Patent number: 7832278
    Abstract: Subject matter disclosed herein may relate to packaging for multi-chip semiconductor devices as may be used, for example, in tire pressure monitoring systems.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: November 16, 2010
    Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.
    Inventors: Man Lung Ivan Sham, Ziyang Gao, Chi Kuen Vincent Leung, Lap Wai Lydia Leung, Lourdito M. Olleres, Chang Hwa Tom Chung
  • Publication number: 20100246141
    Abstract: One aspect of the present invention provides an electronic package, comprising at least a first module and a second module arranged on top of the first module, the modules together in the form of a module stack, wherein the first and second modules are adhesively connected together, each module includes a substrate layer having at least one metal layer, at least one die and a plastic(s) package molding compound layer molded over said die or dice, in each module the die or dice are bonded on said substrate layer via the metal layer, a plurality of channels formed generally vertically acting as vias to connect the metal layers and arranged adjacent to the die or dice in at least one of the modules, some or all the channels provided with an inner surface coated with a conductive material layer or filled with a conductive material for electrical connection whereby the dice are electrically connected together, and means serving as an intermediary for providing electrical, mechanical and thermal connectivity, commu
    Type: Application
    Filed: March 31, 2009
    Publication date: September 30, 2010
    Applicant: Hong Kong Applied Science and Technology Research Institute Co. Ltd. (ASTRI)
    Inventors: Chi Kuen Vincent Leung, Peng Sun, Xunqing Shi, Chang Hwa Chung
  • Publication number: 20090293604
    Abstract: Subject matter disclosed herein may relate to packaging for multi-chip semiconductor devices as may be used, for example, in tire pressure monitoring systems.
    Type: Application
    Filed: May 29, 2008
    Publication date: December 3, 2009
    Applicant: Hong Kong Applied Science and Technology Research Institute Company Limited (ASTRI)
    Inventors: Man Lung Sham, Ziyang Gao, Chi Kuen Vincent Leung, Lap Wai Leung, Lourdito M. Olleres, Chang Hwa Chung
  • Publication number: 20090294974
    Abstract: There is described a bonding method for through-silicon-via bonding of a wafer stack in which the wafers are formed with through-silicon-vias and lateral microchannels that are filled with solder. To fill the vias and channels the wafer stack is placed in a soldering chamber and molten solder is drawn through the vias and channels by vacuum. The wafers are held together by layers of adhesive during the assembly of the wafer stack. Means are provided for local reheating of the solder after it has cooled to soften the solder to enable it to be removed from the soldering chamber.
    Type: Application
    Filed: June 2, 2008
    Publication date: December 3, 2009
    Inventors: Chi Keun Vincent Leung, Peng Sun, Xunqing Shi, Chang Hwa Chung
  • Patent number: 7598769
    Abstract: A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2N configuration bit inputs and a Look Up Table output. The first stage of the Look Up Table includes 2N tri-state buffers coupled to receive the 2N configuration bit inputs respectively. A decoder, configured from logic gates, is coupled to receive to one or more Look Up Table select signals and to generate a set of control signals to control the 2N tri-state buffers so that one or more of the 2N configuration bit inputs is selected by the first stage. The configuration bits are then provided to subsequent muxing stages in the Look Up Table.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: October 6, 2009
    Assignee: Altera Corporation
    Inventor: Vincent Leung
  • Patent number: 7557617
    Abstract: A digital decoder is provided that produces true and complementary output signals. The digital decoder may be formed from n-channel and p-channel metal-oxide-semiconductor transistors. The digital decoder produces four true outputs and four complementary outputs from two inputs. A first of the true outputs and a first of the complementary outputs are provided using a NOR gate and an inverter. A NAND gate and an inverter are used to provide a second of the true outputs and a second of the complementary outputs. Third and fourth complementary outputs are produced using first and second logic circuits. The first and second logic circuits are powered using only a positive power supply voltage. Third and fourth true outputs are produced using third and fourth logic circuits. The third and fourth logic circuits are powered using only a ground power supply voltage. The logic circuits each include an n-channel and p-channel transistor pair.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: July 7, 2009
    Assignee: Altera Corporation
    Inventor: Vincent Leung
  • Publication number: 20080197879
    Abstract: A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2N configuration bit inputs and a Look Up Table output. The first stage of the Look Up Table includes 2N tri-state buffers coupled to receive the 2N configuration bit inputs respectively. A decoder, configured from logic gates, is coupled to receive to one or more Look Up Table select signals and to generate a set of control signals to control the 2N tri-state buffers so that one or more of the 2N configuration bit inputs is selected by the first stage. The configuration bits are then provided to subsequent muxing stages in the Look Up Table.
    Type: Application
    Filed: February 15, 2007
    Publication date: August 21, 2008
    Applicant: Altera Corporation
    Inventor: Vincent Leung
  • Publication number: 20080076378
    Abstract: In one embodiment, a method includes detecting a power level of a power amplifier coupled to a transceiver during a current burst of a radio communication and providing the detected power level from the power amplifier to the transceiver and controlling a power level of the power amplifier during a next burst based on the detected power level of the current burst.
    Type: Application
    Filed: December 27, 2006
    Publication date: March 27, 2008
    Inventors: Lysander Lim, David Pehlke, John Khoury, Vincent Leung
  • Publication number: 20070252646
    Abstract: An adaptive bias method and circuits for amplifiers that provide a substantial current boost based at least partly upon a sensed input power of an amplifier circuit. Methods and circuits of the invention provide an additional bias current based upon the sensed input power. Circuits of the invention may be simple, area-efficient, low-power, stable and digitally-programmable. In addition, methods and circuits of the invention may be used with a number of amplifier circuit configurations, including amplifiers having either inductor and/or resistive degeneration.
    Type: Application
    Filed: February 14, 2005
    Publication date: November 1, 2007
    Inventors: Vincent Leung, Prasad Gudem, Lawrence Larsen
  • Publication number: 20070147040
    Abstract: A reflector/concentrator for a compact fluorescent lamp includes a concave reflector sized to hold a compact fluorescent lamp and having an opening at one end and a central longitudinal axis passing through the opening. The reflector has an internal reflective surface surrounding the axis and providing multiple focal points substantially along the axis from which light emanating from the compact fluorescent lamp can be reflected by the surface through the opening. There is a lens at or adjacent to the opening through which the reflected light passes.
    Type: Application
    Filed: December 27, 2005
    Publication date: June 28, 2007
    Inventor: Vincent Leung
  • Publication number: 20060188417
    Abstract: System and method are disclosed for increasing the effectiveness of the lower tubes in a delayed coker furnace. The system and method involve arranging the tubes so that the lower tubes are as close to the heat source as the upper tubes. Such an arrangement allows all the tubes to have substantially the same amount of radiant flux. In some implementations, it is also possible to conform the refractory floor to the arrangement of the tubes.
    Type: Application
    Filed: February 23, 2005
    Publication date: August 24, 2006
    Inventors: James Roth, Vincent Leung, Brian Doerksen, Robin McGlynn
  • Patent number: D449437
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: October 23, 2001
    Assignee: Masterwise International Limited
    Inventor: Vincent Leung