Patents by Inventor Vincent Paneccasio

Vincent Paneccasio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10541140
    Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: January 21, 2020
    Assignee: MACDERMID ENTHONE INC.
    Inventors: Thomas B. Richardson, Joseph A. Abys, Wenbo Shao, Chen Wang, Vincent Paneccasio, Jr., Cai Wang, Xuan Lin, Theodore Antonellis
  • Patent number: 10519557
    Abstract: An aqueous electrolytic composition and a process for electrodeposition of copper on a dielectric or semiconductor base structure using the aqueous electrolytic composition. The process includes (i) contacting a metalizing substrate comprising a seminal conductive layer on the base structure with an aqueous electrolytic deposition composition; and (ii) supplying electrical current to the electrolytic deposition composition to deposit copper on the substrate.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: December 31, 2019
    Assignee: MacDermid Enthone Inc.
    Inventors: Vincent Paneccasio, Jr., Kyle Whitten, Thomas B. Richardson, Ivan Li
  • Publication number: 20190390356
    Abstract: An electrolytic plating composition for superfilling submicron features in a semiconductor integrated circuit device and a method of using the same. The composition comprises (a) a source of copper ions to electrolytically deposit copper onto the substrate and into the electrical interconnect features, and (b) a suppressor comprising at least three amine sites, said polyether comprising a block copolymer substituent comprising propylene oxide (PO) repeat units and ethylene oxide (EO) repeat units, wherein the number average molecular weight of the suppressor compound is between about 1,000 and about 20,000.
    Type: Application
    Filed: September 21, 2017
    Publication date: December 26, 2019
    Inventors: Vincent Paneccasio, Jr., Kyle Whitten, Richard Hurtubise, John Commander, Eric Rouya
  • Publication number: 20190368064
    Abstract: An electrodeposition composition comprising: (a) a source of copper ions; (b) an acid; (c) a suppressor, and (d) a leveler, wherein the leveler comprises a quaternized dipyridyl compound prepared by reacting a dipyridyl compound with a difunctional alkylating agent or a quaternized poly(epihalohydrin). The electrodeposition composition can be used in a process for forming a copper feature over a semiconductor substrate in wafer level packaging to electrodeposit a copper bump or pillar on an underbump structure of a semiconductor assembly.
    Type: Application
    Filed: September 20, 2017
    Publication date: December 5, 2019
    Inventors: Thomas Richardson, Kyle Whitten, Vincent Paneccasio, Jr., John Commander, Richard Hurtubise
  • Patent number: 10294574
    Abstract: A composition for electrolytic plating in microelectronics which contains a leveler that comprises the reaction product of an aliphatic di(t-amine) with an alkylating agent. Electrolytic plating methods employing the leveler, a method for making the leveler, and the leveler compound.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: May 21, 2019
    Assignee: MacDermid Enthone Inc.
    Inventors: Kyle Whitten, Vincent Paneccasio, Jr., Thomas Richardson, Eric Rouya
  • Patent number: 10221496
    Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: March 5, 2019
    Assignee: MacDermid Enthone Inc.
    Inventors: Thomas B. Richardson, Wenbo Shao, Xuan Lin, Cai Wang, Vincent Paneccasio, Jr., Joseph A. Abys, Yun Zhang, Richard Hurtubise, Chen Wang
  • Publication number: 20190010624
    Abstract: Compositions and methods of using such compositions for electroplating cobalt onto semiconductor base structures comprising submicron-sized electrical interconnect features are provided herein. The interconnect features are metallized by contacting the semiconductor base structure with an electrolytic composition comprising a source of cobalt ions, a suppressor, a buffer, and one or more of a depolarizing compound and a uniformity enhancer. Electrical current is supplied to the electrolytic composition to deposit cobalt onto the base structure and fill the submicron-sized features with cobalt. The method presented herein is useful for superfilling interconnect features.
    Type: Application
    Filed: July 5, 2017
    Publication date: January 10, 2019
    Inventors: John Commander, Kyle Whitten, Vincent Paneccasio, JR., Shaopeng Sun, Eric Yakobson
  • Publication number: 20190003068
    Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.
    Type: Application
    Filed: May 24, 2011
    Publication date: January 3, 2019
    Applicant: ENTHONE INC.
    Inventors: Thomas B. Richardson, Wenbo Shao, Xuan Lin, Cai Wang, Vincent Paneccasio, JR., Joseph A. Abys, Yun Zhang, Richard Hurtubise, Chen Wang
  • Patent number: 10103029
    Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: October 16, 2018
    Assignee: MacDermid Enthone Inc.
    Inventors: Thomas B. Richardson, Joseph A. Abys, Wenbo Shao, Chen Wang, Vincent Paneccasio, Cai Wang, Sean Xuan Lin, Theodore Antonellis
  • Publication number: 20170233883
    Abstract: An aqueous electrolytic composition and a process for electrodeposition of copper on a dielectric or semiconductor base structure using the aqueous electrolytic composition. The process includes (i) contacting a metalizing substrate comprising a seminal conductive layer on the base structure with an aqueous electrolytic deposition composition; and (ii) supplying electrical current to the electrolytic deposition composition to deposit copper on the substrate.
    Type: Application
    Filed: January 23, 2017
    Publication date: August 17, 2017
    Inventors: Vincent Paneccasio, JR., Kyle Whitten, Thomas B. Richardson, Ivan Li
  • Patent number: 9613858
    Abstract: A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: April 4, 2017
    Inventors: Vincent Paneccasio, Jr., Xuan Lin, Richard Hurtubise, Qingyun Chen
  • Publication number: 20170029972
    Abstract: A method and composition for electroplating Cu onto a substrate in the manufacture of a microelectronic device involving and electrolytic solution containing a source of Cu ions and a a quaternized pyridinium salt compound for leveling.
    Type: Application
    Filed: October 12, 2016
    Publication date: February 2, 2017
    Inventors: Vincent Paneccasio, JR., Richard Hurtubise, Xuan Lin, Paul Figura
  • Patent number: 9493884
    Abstract: A method and composition for electroplating Cu onto a substrate in the manufacture of a microelectronic device involving and electrolytic solution containing a source of Cu ions and a quaternized pyridinium salt compound for leveling.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: November 15, 2016
    Inventors: Vincent Paneccasio, Jr., Richard Hurtubise, Xuan Lin, Paul Figura
  • Publication number: 20160281251
    Abstract: In electrolytic copper plating, an aqueous composition comprising a source of copper ions and at least one alkylene or polyalkylene glycol monoether which is soluble in the aqueous phase and has molecular weight not greater than about 500 for improving the efficacy of other additives such as, for example, levelers and suppressors; and a related plating method.
    Type: Application
    Filed: November 25, 2014
    Publication date: September 29, 2016
    Inventors: Vincent Paneccasio, Kyle Whitten, John Commander, Richard Hurtubise, Eric Rouya
  • Publication number: 20160254156
    Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.
    Type: Application
    Filed: May 6, 2016
    Publication date: September 1, 2016
    Inventors: Thomas B. Richardson, Joseph A. Abys, Wenbo Shao, Chen Wang, Vincent Paneccasio, Cai Wang, Xuan Lin, Theodore Antonellis
  • Publication number: 20160076160
    Abstract: A composition for electrolytic plating in microelectronics which contains a leveler that comprises the reaction product of an aliphatic di(t-amine) with an alkylating agent. Electrolytic plating methods employing the leveler, a method for making the leveler, and the leveler compound.
    Type: Application
    Filed: September 15, 2015
    Publication date: March 17, 2016
    Applicant: ENTHONE INC.
    Inventors: Kyle Whitten, Vincent Paneccasio, JR., Thomas Richardson, Eric Rouya
  • Patent number: 9222188
    Abstract: A method for electroplating a copper deposit onto a semiconductor integrated circuit device substrate having submicron-sized features, and a concentrate for forming a corresponding electroplating bath. A substrate is immersed into an electroplating bath formed from the concentrate including ionic copper and an effective amount of a defect reducing agent, and electroplating the copper deposit from the bath onto the substrate to fill the submicron-sized reliefs. The occurrence of protrusion defects from superfilling, surface roughness, and voiding due to uneven growth are reduced, and macro-scale planarity across the wafer is improved.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: December 29, 2015
    Assignee: Enthone Inc.
    Inventors: John Commander, Richard Hurtubise, Vincent Paneccasio, Xuan Lin, Kshama Jirage
  • Publication number: 20140322912
    Abstract: A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.
    Type: Application
    Filed: July 8, 2014
    Publication date: October 30, 2014
    Applicant: Enthone Inc.
    Inventors: Vincent Paneccasio, JR., Xuan Lin, Richard Hurtubise, Qingyun Chen
  • Patent number: 8771495
    Abstract: A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: July 8, 2014
    Assignee: Enthone Inc.
    Inventors: Vincent Paneccasio, Jr., Xuan Lin, Richard Hurtubise, Qingyun Chen
  • Publication number: 20140120722
    Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.
    Type: Application
    Filed: January 26, 2012
    Publication date: May 1, 2014
    Applicant: ENTHONE INC.
    Inventors: Thomas B. Richardson, Joseph A. Abys, Wenbo Shao, Chen Wang, Vincent Paneccasio, JR., Cai Wang, Xuan Lin, Theodore Antonellis