Abstract: A nickel electrodeposition composition for via fill or barrier nickel interconnect fabrication comprising: (a) a source of nickel ions; (b) one or more polarizing additives; and (c) one or more depolarizing additives. The nickel electrodeposition composition may include various additives, including suitable acids, surfactants, buffers, and/or stress modifiers to produce bottom-up filling of vias and trenches.

Abstract: An aqueous electrolytic composition and a process for electrodeposition of copper on a dielectric or semiconductor base structure using the aqueous electrolytic composition. The process includes (i) contacting a metalizing substrate comprising a seminal conductive layer on the base structure with an aqueous electrolytic deposition composition; and (ii) supplying electrical current to the electrolytic deposition composition to deposit copper on the substrate.

Abstract: An aqueous electrolytic composition and a process for electrodeposition of copper on a dielectric or semiconductor base structure using the aqueous electrolytic composition. The process includes (i) contacting a metalizing substrate comprising a seminal conductive layer on the base structure with an aqueous electrolytic deposition composition; and (ii) supplying electrical current to the electrolytic deposition composition to deposit copper on the substrate.

Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.

Abstract: In electrolytic copper plating, an aqueous composition comprising a source of copper ions and at least one alkylene or polyalkylene glycol monoether which is soluble in the aqueous phase and has molecular weight not greater than about 500 for improving the efficacy of other additives such as, for example, levelers and suppressors; and a related plating method.

Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.

Abstract: A method for electroplating a copper deposit onto a semiconductor integrated circuit device substrate having submicron-sized features, and a concentrate for forming a corresponding electroplating bath. A substrate is immersed into an electroplating bath formed from the concentrate including ionic copper and an effective amount of a defect reducing agent, and electroplating the copper deposit from the bath onto the substrate to fill the submicron-sized reliefs. The occurrence of protrusion defects from superfilling, surface roughness, and voiding due to uneven growth are reduced, and macro-scale planarity across the wafer is improved.

Abstract: A method and composition for electroplating Cu onto a substrate in the manufacture of a microelectronic device involving and electrolytic solution containing a source of Cu ions and a substituted pyridyl polymer compound for leveling.

Abstract: A method for plating copper onto a semiconductor integrated circuit device substrate by forming an initial metal deposit in the feature which has a profile comprising metal on the bottom of the feature and a segment of the sidewalls having essentially no metal thereon, electrolessly depositing copper onto the initial metal deposit to fill the feature with copper. A method for plating copper onto a semiconductor integrated circuit device substrate by forming a deposit comprising a copper wettable metal in the feature, forming a copper-based deposit on the top-field surface, and depositing copper onto the deposit comprising the copper wettable metal to fill the feature with copper.

Abstract: A method of preparing an aqueous electroless deposition composition for electrolessly depositing Co or a Co alloy onto a substrate in manufacture of microelectronic devices by treating water or an aqueous electroless deposition composition with a deoxygenating treatment to reduce the oxygen concentration.

Abstract: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Abstract: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Abstract: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Abstract: Cleaning compositions and methods in connection with cobalt-based capping of interconnects in integrated circuit semiconductor devices.

Abstract: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Abstract: A method for electroplating a copper deposit onto a semiconductor integrated circuit device substrate having submicron-sized features, and a concentrate for forming a corresponding electroplating bath. A substrate is immersed into an electroplating bath formed from the concentrate including ionic copper and an effective amount of a defect reducing agent, and electroplating the copper deposit from the bath onto the substrate to fill the submicron-sized reliefs. The occurrence of protrusion defects from superfilling, surface roughness, and voiding due to uneven growth are reduced, and macro-scale planarity across the wafer is improved.

Abstract: A method of preparing an aqueous electroless deposition composition for electrolessly depositing Co or a Co alloy onto a substrate in manufacture of microelectronic devices by treating water or an aqueous electroless deposition composition with a deoxygenating treatment to reduce the oxygen concentration.

Abstract: A method for electroplating a copper deposit onto a semiconductor integrated circuit device substrate having submicron-sized features, and a concentrate for forming a corresponding electroplating bath. A substrate is immersed into an electroplating bath formed from the concentrate including ionic copper and an effective amount of a defect reducing agent, and electroplating the copper deposit from the bath onto the substrate to fill the submicron-sized reliefs. The occurrence of protrusion defects from superfilling, surface roughness, and voiding due to uneven growth are reduced, and macro-scale planarity across the wafer is improved.

Abstract: An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.

Abstract: An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.