Abstract: An electrolytic plating composition for superfilling submicron features in a semiconductor integrated circuit device and a method of using the same. The composition comprises (a) a source of copper ions to electrolytically deposit copper onto the substrate and into the electrical interconnect features, and (b) a suppressor comprising at least three amine sites, said polyether comprising a block copolymer substituent comprising propylene oxide (PO) repeat units and ethylene oxide (EO) repeat units, wherein the number average molecular weight of the suppressor compound is between about 1,000 and about 20,000.

Abstract: An electrodeposition composition comprising: (a) a source of copper ions; (b) an acid; (c) a suppressor; and (d) a leveler, wherein the leveler comprises a quaternized dipyridyl compound prepared by reacting a dipyridyl compound with a difunctional alkylating agent or a quaternized poly(epihalohydrin). The electrodeposition composition can be used in a process for forming a copper feature over a semiconductor substrate in wafer level packaging to electrodeposit a copper bump or pillar on an underbump structure of a semiconductor assembly.

Abstract: Processes and compositions for electroplating a cobalt deposit onto a semiconductor base structure comprising sub-micron-sized electrical interconnect features. In the process, a metalizing substrate within the interconnect features is contacted with an electrodeposition composition comprising a source of cobalt ions, an accelerator comprising an organic sulfur compound, an acetylenic suppressor, a buffering agent and water. Electrical current is supplied to the electrolytic composition to deposit cobalt onto the base structure and fill the submicron-sized features with cobalt. The process is effective for superfilling the interconnect features.

Abstract: Compositions and methods of using such compositions for electroplating cobalt onto semiconductor base structures comprising submicron-sized electrical interconnect features are provided herein. The interconnect features are metallized by contacting the semiconductor base structure with an electrolytic composition comprising a source of cobalt ions, a suppressor, a buffer, and one or more of a depolarizing compound and a uniformity enhancer. Electrical current is supplied to the electrolytic composition to deposit cobalt onto the base structure and fill the submicron-sized features with cobalt. The method presented herein is useful for superfilling interconnect features.

Abstract: A nickel electrodeposition composition for via fill or barrier nickel interconnect fabrication comprising: (a) a source of nickel ions; (b) one or more polarizing additives; and (c) one or more depolarizing additives. The nickel electrodeposition composition may include various additives, including suitable acids, surfactants, buffers, and/or stress modifiers to produce bottom-up filling of vias and trenches.

Abstract: An electrodeposition composition comprising: (a) a source of copper ions; (b) an acid; (c) a suppressor; and (d) a leveler, wherein the leveler comprises a quaternized dipyridyl compound prepared by reacting a dipyridyl compound with a difunctional alkylating agent or a quaternized poly(epihalohydrin). The electrodeposition composition can be used in a process for forming a copper feature over a semiconductor substrate in wafer level packaging to electrodeposit a copper bump or pillar on an underbump structure of a semiconductor assembly.

Abstract: Compositions and methods of using such compositions for electroplating cobalt onto semiconductor base structures comprising submicron-sized electrical interconnect features are provided herein. The interconnect features are metallized by contacting the semiconductor base structure with an electrolytic composition comprising a source of cobalt ions, a suppressor, a buffer, and one or more of a depolarizing compound and a uniformity enhancer. Electrical current is supplied to the electrolytic composition to deposit cobalt onto the base structure and fill the submicron-sized features with cobalt. The method presented herein is useful for superfilling interconnect features.

Abstract: An aqueous electrolytic composition and a process for electrodeposition of copper on a dielectric or semiconductor base structure using the aqueous electrolytic compostion. The process includes (i) contacting a metalizing substrate comprising a seminal conductive layer on the base structure with an aqueous electrolytic deposition composition; and (ii) supplying electrical current to the electrolytic deposition composition to deposit copper on the substrate.

Abstract: An electrodeposition composition comprising: (a) a source of copper ions; (b) an acid; (c) a suppressor, and (d) a leveler, wherein the leveler comprises a quaternized dipyridyl compound prepared by reacting a dipyridyl compound with a difunctional alkylating agent or a quaternized poly(epihalohydrin). The electrodeposition composition can be used in a process for forming a copper feature over a semiconductor substrate in wafer level packaging to electrodeposit a copper bump or pillar on an underbump structure of a semiconductor assembly.

Abstract: Processes and compositions for electroplating a cobalt deposit onto a semiconductor base structure comprising sub-micron-sized electrical interconnect features. In the process, a metalizing substrate within the interconnect features is contacted with an electrodeposition composition comprising a source of cobalt ions, an accelerator comprising an organic sulfur compound, an acetylenic suppressor, a buffering agent and water. Electrical current is supplied to the electrolytic composition to deposit cobalt onto the base structure and fill the submicron-sized features with cobalt. The process is effective for superfilling the interconnect features.

Abstract: Compositions and methods of using such compositions for electroplating cobalt onto semiconductor base structures comprising submicron-sized electrical interconnect features are provided herein. The interconnect features are metallized by contacting the semiconductor base structure with an electrolytic composition comprising a source of cobalt ions, a suppressor, a buffer, and one or more of a depolarizing compound and a uniformity enhancer. Electrical current is supplied to the electrolytic composition to deposit cobalt onto the base structure and fill the submicron-sized features with cobalt. The method presented herein is useful for superfilling interconnect features.

Abstract: Processes and compositions for electroplating a cobalt deposit onto a semiconductor base structure comprising submicron-sized electrical interconnect features. In the process, a metalizing substrate within the interconnect features is contacted with an electrodeposition composition comprising a source of cobalt ions, an accelerator comprising an organic sulfur compound, an acetylenic suppressor, a buffering agent and water. Electrical current is supplied to the electrolytic composition to deposit cobalt onto the base structure and fill the submicron-sized features with cobalt. The process is effective for superfilling the interconnect features.

Abstract: Processes and compositions for electroplating a cobalt deposit onto a semiconductor base structure comprising submicron-sized electrical interconnect features. In the process, a metalizing substrate within the interconnect features is contacted with an electrodeposition composition comprising a source of cobalt ions, an accelerator comprising an organic sulfur compound, an acetylenic suppressor, a buffering agent and water. Electrical current is supplied to the electrolytic composition to deposit cobalt onto the base structure and fill the submicron-sized features with cobalt. The process is effective for superfilling the interconnect features.

Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.

Abstract: An aqueous electrolytic composition and a process for electrodeposition of copper on a dielectric or semiconductor base structure using the aqueous electrolytic composition. The process includes (i) contacting a metalizing substrate comprising a seminal conductive layer on the base structure with an aqueous electrolytic deposition composition; and (ii) supplying electrical current to the electrolytic deposition composition to deposit copper on the substrate.

Abstract: An electrolytic plating composition for superfilling submicron features in a semiconductor integrated circuit device and a method of using the same. The composition comprises (a) a source of copper ions to electrolytically deposit copper onto the substrate and into the electrical interconnect features, and (b) a suppressor comprising at least three amine sites, said polyether comprising a block copolymer substituent comprising propylene oxide (PO) repeat units and ethylene oxide (EO) repeat units, wherein the number average molecular weight of the suppressor compound is between about 1,000 and about 20,000.

Abstract: An electrodeposition composition comprising: (a) a source of copper ions; (b) an acid; (c) a suppressor, and (d) a leveler, wherein the leveler comprises a quaternized dipyridyl compound prepared by reacting a dipyridyl compound with a difunctional alkylating agent or a quaternized poly(epihalohydrin). The electrodeposition composition can be used in a process for forming a copper feature over a semiconductor substrate in wafer level packaging to electrodeposit a copper bump or pillar on an underbump structure of a semiconductor assembly.

Abstract: A composition for electrolytic plating in microelectronics which contains a leveler that comprises the reaction product of an aliphatic di(t-amine) with an alkylating agent. Electrolytic plating methods employing the leveler, a method for making the leveler, and the leveler compound.

Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.

Abstract: An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.