Abstract: Circuitry for providing an oscillating output signal. The circuitry comprises a transconductance circuit having a first input, a second input, and an output. The circuitry further comprises an oscillator circuit coupled to receive voltage from the output of the transconductance circuit, wherein the oscillating output signal is responsive to an output of the oscillator circuit. Also included are circuitry for providing a first voltage to the first input of the transconductance circuit and a frequency controlled circuit for providing a second voltage to the second input the transconductance circuit. The second voltage is response to a frequency of operation of the frequency controlled circuit, and the frequency of operation of the frequency controlled circuit is responsive to feedback from the output of the oscillator circuit.

Abstract: Circuitry for providing an oscillating output signal. The circuitry comprises a transconductance circuit having a first input, a second input, and an output. The circuitry further comprises an oscillator circuit coupled to receive voltage from the output of the transconductance circuit, wherein the oscillating output signal is responsive to an output of the oscillator circuit. Also included are circuitry for providing a first voltage to the first input of the transconductance circuit and a frequency controlled circuit for providing a second voltage to the second input the transconductance circuit. The second voltage is response to a frequency of operation of the frequency controlled circuit, and the frequency of operation of the frequency controlled circuit is responsive to feedback from the output of the oscillator circuit.

Abstract: Circuits and methods for reducing input dependent capacitor DAC switching current in flash-successive approximation register (SAR) analog-to-digital converters (ADCs) are disclosed. An ADC includes an M-bit flash ADC and N-bit SAR ADC. In flash conversion phase, flash ADC outputs digital signal including most significant M-bits of N-bits of digital output code for a sampled analog signal. SAR ADC includes capacitor DAC and digital engine. The capacitor DAC includes first and second set of capacitors, where first ends of the first and second set of capacitors are coupled to common terminal. The digital engine provides the N-bits of digital output code in SAR conversion phase based on the digital signal and a voltage (Vcom) at the common terminal. During flash conversion phase, second ends of the first set of capacitors are connected to Vref and Vgnd respectively so as to generate a voltage level corresponding to the digital signal as Vcom.

Abstract: Circuits and methods for reducing input dependent capacitor DAC switching current in flash-successive approximation register (SAR) analog-to-digital converters (ADCs) are disclosed. An ADC includes an M-bit flash ADC and N-bit SAR ADC. In flash conversion phase, flash ADC outputs digital signal including most significant M-bits of N-bits of digital output code for a sampled analog signal. SAR ADC includes capacitor DAC and digital engine. The capacitor DAC includes first and second set of capacitors, where first ends of the first and second set of capacitors are coupled to common terminal. The digital engine provides the N-bits of digital output code in SAR conversion phase based on the digital signal and a voltage (Vcom) at the common terminal. During flash conversion phase, second ends of the first set of capacitors are connected to Vref and Vgnd respectively so as to generate a voltage level corresponding to the digital signal as Vcom.

Abstract: A driver circuit includes a first driver amplifier that is configured to generate a first output in response to a first reference voltage input and a first audio input; a second driver amplifier that is configured to generate a second output in response to the first reference voltage and a second audio input; and a common mode (CM) amplifier, coupled to the first driver amplifier and the second driver amplifier. The CM amplifier is configured to generate an output in response to a second reference voltage input, the first reference voltage input being a divided version of the output. Gains of the first driver amplifier, second driver amplifier and the CM amplifier are equal. Noise at the output appears across a plurality of resistors coupled at the outputs of the first driver amplifier, second driver amplifier and the CM amplifier and cancels with respect to the output of the CM amplifier.

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract: An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.

Abstract: A continuous-time sigma-delta analog to digital converter (CTSD ADC) includes a comparator that samples the time integral of an analog signal at each rising edge and falling edge of a sampling clock. A feedback block, operating as a digital to analog converter, receives the outputs of the comparator and generates corresponding analog signals also at each rising and falling edge of the sampling clock. The feedback blocks are implemented as either switched-resistor or switched-current circuits. High signal-to-noise ratio (SNR) is achieved in the CTSD ADC without the need to use very high sampling clock frequencies. Compensation for excess loop delay is provided using a local feedback technique. In an embodiment, the sigma delta modulator in the CTSD ADC is implemented as a second order loop, and the comparator as a two-level comparator.

Abstract: A continuous-time sigma-delta analog to digital converter (CTSD ADC) includes a comparator that samples the time integral of an analog signal at each rising edge and falling edge of a sampling clock. A feedback block, operating as a digital to analog converter, receives the outputs of the comparator and generates corresponding analog signals also at each rising and falling edge of the sampling clock. The feedback blocks are implemented as either switched-resistor or switched-current circuits. High signal-to-noise ratio (SNR) is achieved in the CTSD ADC without the need to use very high sampling clock frequencies. Compensation for excess loop delay is provided using a local feedback technique. In an embodiment, the sigma delta modulator in the CTSD ADC is implemented as a second order loop, and the comparator as a two-level comparator.

Abstract: A driver circuit includes a first driver amplifier that is configured to generate a first output in response to a first reference voltage input and a first audio input; a second driver amplifier that is configured to generate a second output in response to the first reference voltage and a second audio input; and a common mode (CM) amplifier, coupled to the first driver amplifier and the second driver amplifier. The CM amplifier is configured to generate an output in response to a second reference voltage input, the first reference voltage input being a divided version of the output. Gains of the first driver amplifier, second driver amplifier and the CM amplifier are equal. Noise at the output appears across a plurality of resistors coupled at the outputs of the first driver amplifier, second driver amplifier and the CM amplifier and cancels with respect to the output of the CM amplifier.

Abstract: An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.

Abstract: An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.

Abstract: An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.

Abstract: A low noise current steering digital-to-analog converter (DAC). The DAC includes a current reference for generating a bias current that biases a set of current elements. The set of current elements includes a reference element. The current reference includes a reference amplifier and a reference arm. The reference arm includes a reference resistor and the reference element. The DAC further includes a switch periodically coupling each current element including the reference element, to the reference resistor and an output of the DAC. This rotates the set of current elements and attenuates flicker noise from each of the set of current elements.

Abstract: A low noise current steering digital-to-analog converter (DAC). The DAC includes a current reference for generating a bias current that biases a set of current elements. The set of current elements includes a reference element. The current reference includes a reference amplifier and a reference arm. The reference arm includes a reference resistor and the reference element. The DAC further includes a switch periodically coupling each current element including the reference element, to the reference resistor and an output of the DAC. This rotates the set of current elements and attenuates flicker noise from each of the set of current elements.

Abstract: A method and system is provided for determining noise components of an analog-to-digital converter. In one aspect of the invention, a method comprises providing an input signal to a signal input and a clock input of the ADC, outputting a plurality of samples at a sampled phase on the input signal for a plurality of sampled phases, and determining a jitter noise factor value, a reference noise factor value, and a total noise spectrum based on the plurality of samples for each of the plurality of sampled phases. A least means square algorithm is performed on the plurality of jitter noise factor values, reference noise factor values, and total noise spectra to estimate at least one of a jitter noise component and a reference noise component.

Abstract: A clamping circuit containing a transistor and a current amplifier. The transistor is designed to turn on when the voltage at a node exceeds (falls below) a specified upper (lower) level. The current amplifier is designed to draw substantial amount of current when the transistor is turned on to clamp the voltage at the node to the desired level.