Abstract: A method and system is provided for determining noise components of an analog-to-digital converter. In one aspect of the invention, a method comprises providing an input signal to a signal input and a clock input of the ADC, outputting a plurality of samples at a sampled phase on the input signal for a plurality of sampled phases, and determining a jitter noise factor value, a reference noise factor value, and a total noise spectrum based on the plurality of samples for each of the plurality of sampled phases. A least means square algorithm is performed on the plurality of jitter noise factor values, reference noise factor values, and total noise spectra to estimate at least one of a jitter noise component and a reference noise component.

Abstract: Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.

Abstract: An ADC implemented according to an aspect of the present invention contains a non-zero bit stage followed by a zero-bit stage. The non-zero bit stage generates a sub-code, which is used in generating a digital code corresponding to an input analog signal, and the zero-bit stage does not provide any such sub-codes. Such a feature may be attained by using a gain amplifier provided according to another aspect of the present invention. The gain amplifier contains a main-amplifier which operates as a zero bit stage, and is also used by the non-zero bit stage. The same capacitance value may be maintained between the input terminal and output terminal of the main-amplifier to implement the zero bit stage, which enables the main-amplifier to be implemented with a low gain.

Abstract: A delay locked loop clock generation circuit (100) includes a delay locked loop circuit (18), a dummy delay line (40), and a watch dog circuit (32). The delay locked loop circuit includes a delay line (20), a phase detector (25), and a charge pump circuit (30) having an input connected to the output (27) of the phase detector and an output (23) producing a delay control signal (Vctrl) coupled to the stages of the delay line of the delay locked loop circuit. The stages of the delay line are precisely matched to those of the dummy delay line (40). Tap points of the dummy delay line are connected to inputs of the watchdog circuit (32), which operates to generate control signals (34A,B) applied to control the phase detector (25 and the charge pump circuit (30). Tap point signals of the delay line (20) are decoded to produce clock signals (52) for a pipeline ADC (54).

Abstract: Generating a waveform having one signal level periodically and different signal levels in other durations. Two input signals are received, one having a desired constant level and another having desired signal levels. The desired output waveform is generated by selecting one of the two input signals. As a result, the output waveform may be generated to have (transitions) with high frequency even if the signal levels between adjacent portions are substantially different. Such waveforms are useful to test CDS (correlated double sampling) samplers.

Abstract: Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.

Abstract: A clamping circuit containing a transistor and a current amplifier. The transistor is designed to turn on when the voltage at a node exceeds (falls below) a specified upper (lower) level. The current amplifier is designed to draw substantial amount of current when the transistor is turned on to clamp the voltage at the node to the desired level.

Abstract: An on-chip calibration circuit which can dynamically (i.e., in operational environment) measure the capacitor mismatch in an ADC using sampling capacitors to sample an input signal and a feedback capacitor (in combination with an amplifier) for amplification. The measured values can be used to generate accurate digital codes representing analog signal samples. The calibration circuit connects the capacitors to various voltage levels and measures the mismatch levels by examining various signals (e.g., the digital codes) generated in such situations.

Abstract: An ADC implemented according to an aspect of the present invention contains a non-zero bit stage followed by a zero-bit stage. The non-zero bit stage generates a sub-code, which is used in generating a digital code corresponding to an input analog signal, and the zero-bit stage does not provide any such sub-codes. Such a feature may be attained by using a gain amplifier provided according to another aspect of the present invention. The gain amplifier contains a main-amplifier which operates as a zero bit stage, and is also used by the non-zero bit stage. The same capacitance value may be maintained between the input terminal and output terminal of the main-amplifier to implement the zero bit stage, which enables the main-amplifier to be implemented with a low gain.

Abstract: A delay locked loop clock generation circuit (100) includes a delay locked loop circuit (18), a dummy delay line (40), and a watch dog circuit (32). The delay locked loop circuit includes a delay line (20), a phase detector (25), and a charge pump circuit (30) having an input connected to the output (27) of the phase detector and an output (23) producing a delay control signal (Vctrl) coupled to the stages of the delay line of the delay locked loop circuit. The stages of the delay line are precisely matched to those of the dummy delay line (40). Tap points of the dummy delay line are connected to inputs of the watchdog circuit (32), which operates to generate control signals (34A,B) applied to control the phase detector (25 and the charge pump circuit (30). Tap point.signals of the delay line (20) are decoded to produce clock signals (52) for a pipeline ADC (54).

Abstract: An on-chip calibration circuit which can dynamically (i.e., in operational environment) measure the capacitor mismatch in an ADC using sampling capacitors to sample an input signal and a feedback capacitor (in combination with an amplifier) for amplification. The measured values can be used to generate accurate digital codes representing analog signal samples. The calibration circuit connects the capacitors to various voltage levels and measures the mismatch levels by examining various signals (e.g., the digital codes) generated in such situations.

Abstract: Generating a waveform having one signal level periodically and different signal levels in other durations. Two input signals are received, one having a desired constant level and another having desired signal levels. The desired output waveform is generated by selecting one of the two input signals. As a result, the output waveform may be generated to have (transitions) with high frequency even if the signal levels between adjacent portions are substantially different. Such waveforms are useful to test CDS (correlated double sampling) samplers.