Abstract: Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In a first program pass of a multi-pass program operation, pass voltages of the word lines adjacent to a selected word line are adjusted to increase electron injection in a portion of a charge-trapping layer between the selected word line and an adjacent source side unselected word line. In a second, final program pass of the multi-pass program operation, the pass voltages are adjusted to reduce electron injection in the portion of the charge-trapping layer between the selected word line and the adjacent source side unselected word line.

Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a refresh operation is performed repeatedly to couple up data word line voltages but not dummy word line voltages. The refresh operation can involve applying a voltage pulse to the data word lines of a block when the block is not being used for a storage operation such as a program, read or erase operation. When the voltage pulse is applied to the data word lines, the dummy word lines can be set to a low level such as 0 V. This low level prevents or limits coupling up of the dummy memory cells to avoid creating an electric field which can cause holes to move from the dummy memory cells to adjacent select gate transistors.

Abstract: Systems, methods, and devices of the various embodiments provide both “string-sharing” drain select gate electrodes and “string-selective” drain select gate electrodes in vertical NAND strings. Various embodiments may provide two or more vertical NAND strings sharing a common drain select gate electrode while also having separate additional drain select gate electrodes not electrically connected across the two or more vertical NAND strings.

Abstract: Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.

Abstract: Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.

Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a refresh operation is performed repeatedly to couple up data word line voltages but not dummy word line voltages. The refresh operation can involve applying a voltage pulse to the data word lines of a block when the block is not being used for a storage operation such as a program, read or erase operation. When the voltage pulse is applied to the data word lines, the dummy word lines can be set to a low level such as 0 V. This low level prevents or limits coupling up of the dummy memory cells to avoid creating an electric field which can cause holes to move from the dummy memory cells to adjacent select gate transistors.

Abstract: Techniques for reducing a downshift in the threshold voltage of a select gate transistor of a memory device. Due to an electric field in a NAND string, holes can move in a charge-trapping layer from a dummy memory cell to a select gate transistor and combine with electrons in the transistor, reducing the threshold voltage. In one approach, the electric field is reduced at the end of a sensing operation by ramping down the voltage of the dummy memory cells before ramping down the voltage of the select gate transistors. The ramp down of the voltage of the selected memory cells can occur after ramping down the voltage of the dummy memory cells and before ramping down of the voltage of the select gate transistors. A further option involves elevating the voltage of the select gate transistors before it is ramped down.

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation. A pre-charge operation occurs in which a channel voltage is increased to a positive level. This reduces a channel gradient which can lead to a disturb of the select gate transistors. One approach involves applying a voltage at an intermediate level to the source and/or drain ends of the memory strings, before increasing the voltage from the intermediate level to a peak erase level. Another approach involves driving the word line voltages at a negative level and then at a higher level to down couple and then up couple the channel voltages. The techniques may be adjusted depending on whether the word lines are at a positive floating voltage at a start of the erase operation, and based on a level of the floating voltage.

Abstract: A memory device and associated techniques for reducing charge loss in a select gate transistor. A dummy memory cell is weakly programmed using a hot electron injection type of disturb to reduce the movement of holes toward the adjacent select gate transistor in a common charge trapping layer. The weak programming can occur in a program loop, e.g., in a transition between a pre-charge phase and a program phase, or in an erase loop, just after the erase of dummy and data memory cells. The weak programming does not involve a time penalty since it is concurrent with other operations. The disturb can be provided by increasing the control gate voltage of the dummy memory cell and/or decreasing the control gate voltage of the select gate transistor.

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel gradient near the select gate transistors is reduced when the voltages of the drain and source ends of a memory string are increased to an erase level which charges up the channel. In one approach, the voltage of the word line which is adjacent to a select gate line is temporarily increased. Another approach builds off the first approach by temporarily increasing the voltage of the select gate line at the same time as the increase in the word line voltage.

Abstract: This is directed to a case for securing and protecting an electronic device. The case can include a cover connected to a pouch by a hinge such that the cover can be overlaid over a device interface (e.g., a device display). The case can be constructed by layering and combining several types of materials, including for example materials having resistant outer surfaces, materials limiting the deformation of the case, materials providing a soft surface to be placed in contact with the device, and rigid materials for defining a structure of the case. In some embodiments, the case can include a tab that allows a user to fold open the cover of the case to form a triangular prism. The prism can be placed on any of its surfaces such that the device can be oriented towards a user at particular angles (e.g., a typing-specific orientation and a media playback orientation).

Abstract: Techniques are provided for reducing program disturb and short term data retention loss. Program disturb becomes worse for the drain-side memory cells at higher temperatures, while data retention generally does not become worse at higher temperatures. In one aspect, a deeper erase is provided for drain-side memory cells when the temperature is relatively high, to reduce program disturb. In another aspect, the verify levels of the programmed data states are lowered to reduce data retention loss when the temperature is relatively high. In another aspect, the number of read errors is used to adjust the depth of the depth of the erase operation. In another aspect, a pass voltage of a drain-side cell is lowered during a verify test for another cell to account for the deep erase of the drain-side cell.

Abstract: Techniques are provided for reducing program disturb and short term data retention loss. Program disturb becomes worse for the drain-side memory cells at higher temperatures, while data retention generally does not become worse at higher temperatures. In one aspect, a deeper erase is provided for drain-side memory cells when the temperature is relatively high, to reduce program disturb. In another aspect, the verify levels of the programmed data states are lowered to reduce data retention loss when the temperature is relatively high. In another aspect, the number of read errors is used to adjust the depth of the depth of the erase operation. In another aspect, a pass voltage of a drain-side cell is lowered during a verify test for another cell to account for the deep erase of the drain-side cell.

Abstract: This is directed to a case for securing and protecting an electronic device. The case can include a cover connected to a pouch by a hinge such that the cover can be overlaid over a device interface (e.g., a device display). The case can be constructed by layering and combining several types of materials, including for example materials having resistant outer surfaces, materials limiting the deformation of the case, materials providing a soft surface to be placed in contact with the device, and rigid materials for defining a structure of the case. In some embodiments, the case can include a tab that allows a user to fold open the cover of the case to form a triangular prism. The prism can be placed on any of its surfaces such that the device can be oriented towards a user at particular angles (e.g., a typing-specific orientation and a media playback orientation).

Abstract: An electronic device may have a housing in which electronic components are mounted. The electronic components may be mounted to a substrate such as a printed circuit board. A heat sink structure may dissipate heat generated by the electronic components. The housing may have a housing wall that is separated from the heat sink structure by an air gap. The housing wall may have integral support structures. Each of the support structures may have an inwardly protruding portion that protrudes through a corresponding opening in the heat sink structure. The protruding portions may each have a longitudinal axis and a cylindrical cavity that lies along the longitudinal axis. Each of the support structures may have fins that extend radially outward from the longitudinal axis.

Abstract: An electronic device may have a housing in which electronic components are mounted. The electronic components may be mounted to a substrate such as a printed circuit board. A heat sink structure may dissipate heat generated by the electronic components. The housing may have a housing wall that is separated from the heat sink structure by an air gap. The housing wall may have integral support structures. Each of the support structures may have an inwardly protruding portion that protrudes through a corresponding opening in the heat sink structure. The protruding portions may each have a longitudinal axis and a cylindrical cavity that lies along the longitudinal axis. Each of the support structures may have fins that extend radially outward from the longitudinal axis.

Abstract: This is directed to a case for securing and protecting an electronic device. The case can include a cover connected to a pouch by a hinge such that the cover can be overlaid over a device interface (e.g., a device display). The case can be constructed by layering and combining several types of materials, including for example materials having resistant outer surfaces, materials limiting the deformation of the case, materials providing a soft surface to be placed in contact with the device, and rigid materials for defining a structure of the case. In some embodiments, the case can include a tab that allows a user to fold open the cover of the case to form a triangular prism. The prism can be placed on any of its surfaces such that the device can be oriented towards a user at particular angles (e.g., a typing-specific orientation and a media playback orientation).

Abstract: An electronic device may have a housing in which electronic components are mounted. The electronic components may be mounted to a substrate such as a printed circuit board. A heat sink structure may dissipate heat generated by the electronic components. The housing may have a housing wall that is separated from the heat sink structure by an air gap. The housing wall may have integral support structures. Each of the support structures may have an inwardly protruding portion that protrudes through a corresponding opening in the heat sink structure. The protruding portions may each have a longitudinal axis and a cylindrical cavity that lies along the longitudinal axis. Each of the support structures may have fins that extend radially outward from the longitudinal axis.