Patents by Inventor Vinod Adivarahan

Vinod Adivarahan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9985177
    Abstract: An ultraviolet light emitting semiconductor chip, its use in a LED, and methods of its fabrication are disclosed. The semiconductor chip can include a buffer layer of AlxGa1-xN, where 0<x?1 having a thickness from about 10 ?m to about 3 mm and defining apertures in the thickness of the buffer layer formed due to lateral overgrowth of the buffer layer over a grooved basal substrate. A n-junction LED layer overlying the buffer layer, a multiple quantum well LED layer overlying the n-junction LED layer, and a p-junction LED layer overlying the multiple quantum well LED layer are also included in the chip, where all of the LED layers comprise AlxGa1-xN, where 0<x?1.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: May 29, 2018
    Assignee: University of South Carolina
    Inventors: M. Asif Khan, Qhalid Fareed, Vinod Adivarahan
  • Patent number: 9882039
    Abstract: Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: January 30, 2018
    Assignee: University of South Carolina
    Inventors: M. Asif Khan, Vinod Adivarahan
  • Patent number: 9859457
    Abstract: A template for a semiconductor device is made by providing an AGN substrate, growing a first layer of Group III nitrides on the substrate, depositing a thin metal layer on the first layer, annealing the metal such as gold so that it agglomerates to form a pattern of islands on the first layer; transferring the pattern into the first layer by etching then removing excess metal; and then depositing a second Group III nitride layer on the first layer. The second layer, through lateral overgrowth, coalesces over the gaps in the island pattern leaving a smooth surface with low defect density. A Group III semiconductor device may then be grown on the template, which may then be removed. Chlorine gas may be used for etching the pattern in the first layer and the remaining gold removed with aqua regia.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: January 2, 2018
    Assignee: Nitek, Inc.
    Inventors: Vinod Adivarahan, Asif Khan, Iftikhar Ahmad, Bin Zhang, Alexander Lunev
  • Patent number: 9543425
    Abstract: MOSHFET devices are provided, along with their methods of fabrication. The MOSHFET device can include a substrate; a multilayer stack on the substrate; a ultra-thin barrier layer on the multilayer stack, wherein the ultra-thin barrier layer has a thickness of about 0.5 nm to about 10 nm; a dielectric, discontinuous thin film layer on portions of the ultra-thin barrier layer, wherein the dielectric, discontinuous thin film layer comprises SiO2; a plurality of source electrodes and drain electrodes formed directly on the ultra-thin barrier layer in an alternating pattern such that the dielectric, discontinuous thin film layer is positioned between adjacent source electrodes and drain electrodes; a plurality of gate electrodes on the dielectric, discontinuous thin film layer; and a gate interconnect electrically connecting the plurality of gate electrodes.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: January 10, 2017
    Assignee: University of South Carolina
    Inventors: Asif Khan, Vinod Adivarahan
  • Publication number: 20160276533
    Abstract: An ultraviolet light emitting semiconductor chip, its use in a LED, and methods of its fabrication are disclosed. The semiconductor chip can include a buffer layer of AlxGa1-xN, where 0<x?1 having a thickness from about 10 ?m to about 3 mm and defining apertures in the thickness of the buffer layer formed due to lateral overgrowth of the buffer layer over a grooved basal substrate. A n-junction LED layer overlying the buffer layer, a multiple quantum well LED layer overlying the n-junction LED layer, and a p-junction LED layer overlying the multiple quantum well LED layer are also included in the chip, where all of the LED layers comprise AlxGa1-xN, where 0<x?1.
    Type: Application
    Filed: March 22, 2016
    Publication date: September 22, 2016
    Inventors: M. Asif Khan, Qhalid Fareed, Vinod Adivarahan
  • Publication number: 20160240647
    Abstract: MOSHFET devices are provided, along with their methods of fabrication. The MOSHFET device can include a substrate; a multilayer stack on the substrate; a ultra-thin barrier layer on the multilayer stack, wherein the ultra-thin barrier layer has a thickness of about 0.5 nm to about 10 nm; a dielectric, discontinuous thin film layer on portions of the ultra-thin barrier layer, wherein the dielectric, discontinuous thin film layer comprises SiO2; a plurality of source electrodes and drain electrodes formed directly on the ultra-thin barrier layer in an alternating pattern such that the dielectric, discontinuous thin film layer is positioned between adjacent source electrodes and drain electrodes; a plurality of gate electrodes on the dielectric, discontinuous thin film layer; and a gate interconnect electrically connecting the plurality of gate electrodes.
    Type: Application
    Filed: April 25, 2016
    Publication date: August 18, 2016
    Inventors: Asif Khan, Vinod Adivarahan
  • Patent number: 9343544
    Abstract: MOSHFET devices are provided, along with their methods of fabrication. The MOSHFET device can include a substrate; a multilayer stack on the substrate; a ultra-thin barrier layer on the multilayer stack, wherein the ultra-thin barrier layer has a thickness of about 0.5 nm to about 10 nm; a dielectric, discontinuous thin film layer on portions of the ultra-thin barrier layer, wherein the dielectric, discontinuous thin film layer comprises SiO2; a plurality of source electrodes and drain electrodes formed directly on the ultra-thin barrier layer in an alternating pattern such that the dielectric, discontinuous thin film layer is positioned between adjacent source electrodes and drain electrodes; a plurality of gate electrodes on the dielectric, discontinuous thin film layer; and a gate interconnect electrically connecting the plurality of gate electrodes.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: May 17, 2016
    Assignee: University of South Carolina
    Inventors: Asif Khan, Vinod Adivarahan
  • Patent number: 9343563
    Abstract: Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: May 17, 2016
    Assignee: University of South Carolina
    Inventors: Asif Khan, Qhalid Fareed, Vinod Adivarahan
  • Patent number: 9331240
    Abstract: An ultraviolet light emitting semiconductor chip, its use in a LED, and methods of its fabrication are disclosed. The semiconductor chip can include a buffer layer of AlxGa1-xN, where 0<x?1 having a thickness from about 10 ?m to about 3 mm and defining apertures in the thickness of the buffer layer formed due to lateral overgrowth of the buffer layer over a grooved basal substrate. A n-junction LED layer overlying the buffer layer, a multiple quantum well LED layer overlying the n-junction LED layer, and a p-junction LED layer overlying the multiple quantum well LED layer are also included in the chip, where all of the LED layers comprise AlxGa1-xN, where 0<x?1.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: May 3, 2016
    Assignee: University of South Carolina
    Inventors: M. Asif Khan, Qhalid Fareed, Vinod Adivarahan
  • Publication number: 20150270382
    Abstract: MOSHFET devices are provided, along with their methods of fabrication. The MOSHFET device can include a substrate; a multilayer stack on the substrate; a ultra-thin barrier layer on the multilayer stack, wherein the ultra-thin barrier layer has a thickness of about 0.5 nm to about 10 nm; a dielectric, discontinuous thin film layer on portions of the ultra-thin barrier layer, wherein the dielectric, discontinuous thin film layer comprises SiO2; a plurality of source electrodes and drain electrodes formed directly on the ultra-thin barrier layer in an alternating pattern such that the dielectric, discontinuous thin film layer is positioned between adjacent source electrodes and drain electrodes; a plurality of gate electrodes on the dielectric, discontinuous thin film layer; and a gate interconnect electrically connecting the plurality of gate electrodes.
    Type: Application
    Filed: March 24, 2015
    Publication date: September 24, 2015
    Inventors: Asif Khan, Vinod Adivarahan
  • Patent number: 9142714
    Abstract: An improved process for forming a UV emitting diode is described. The process includes providing a substrate. A super-lattice is formed directly on the substrate at a temperature of at least 800 to no more than 1,300° C. wherein the super-lattice comprises AlxInyGa1-x-yN wherein 0<x?1, 0?y?1 and 0<x+y?1. A first conductive layer with a first type of conductivity is formed on the super-lattice wherein the first conductive layer comprises AlxInyGa1-x-yN wherein 0<x?1, 0?y?1 and 0<x+y?1. A quantum well region is formed on the first conductive layer wherein the quantum well region comprises AlxInyGa1-x-yN wherein 0<x?1, 0?y?1 and 0<x+y?1. A second conductive layer is formed on the quantum well with a second type of conductivity wherein the second conductive layer comprises AlxInyGa1-x-yN wherein 0<x?1, 0?y?1 and 0<x+y?1.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: September 22, 2015
    Assignee: NITEK, INC.
    Inventors: Vinod Adivarahan, Qhalid Fareed, Asif Khan
  • Publication number: 20150263221
    Abstract: A template for a semiconductor device is made by providing an AGN substrate, growing a first layer of Group III nitrides on the substrate, depositing a thin metal layer on the first layer, annealing the metal such as gold so that it agglomerates to form a pattern of islands on the first layer; transferring the pattern into the first layer by etching then removing excess metal; and then depositing a second Group III nitride layer on the first layer. The second layer, through lateral overgrowth, coalesces over the gaps in the island pattern leaving a smooth surface with low defect density. A Group III semiconductor device may then be grown on the template, which may then be removed. Chlorine gas may be used for etching the pattern in the first layer and the remaining gold removed with aqua regia.
    Type: Application
    Filed: May 18, 2015
    Publication date: September 17, 2015
    Inventors: Vinod Adivarahan, Asif KHAN, Iftikhar Ahmad, Bin Zhang, Alexander Lunev
  • Patent number: 9059081
    Abstract: The present invention is generally directed to methods of selectively doping a substrate and the resulting selectively doped substrates. The methods include doping an epilayer of a substrate with the selected doping material to adjust the conductivity of either the epilayers grown over a substrate or the substrate itself. The methods utilize lithography to control the location of the doped regions on the substrate. The process steps can be repeated to form a cyclic method of selectively doping different areas of the substrate with the same or different doping materials to further adjust the properties of the resulting substrate.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: June 16, 2015
    Assignee: University of South Carolina
    Inventors: Asif Khan, Vinod Adivarahan
  • Publication number: 20150001550
    Abstract: Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.
    Type: Application
    Filed: August 4, 2014
    Publication date: January 1, 2015
    Inventors: Asif Khan, Qhalid Fareed, Vinod Adivarahan
  • Patent number: 8796097
    Abstract: Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: August 5, 2014
    Assignee: University of South Carolina
    Inventors: Asif Khan, Qhalid Fareed, Vinod Adivarahan
  • Patent number: 8698191
    Abstract: Ultraviolet light emitting illuminator, and method for fabricating same, comprises an array of ultraviolet light emitting diodes and a first and second terminal. When an alternating current is applied across the first and second terminals and thus to each of the diodes, the illuminator emits ultraviolet light at a frequency corresponding to that of the alternating current. The illuminator includes a template with ultraviolet light emitting quantum wells, a first buffer layer with a first type of conductivity and a second buffer layer with a second type of conductivity, all deposited preferably over strain-relieving layer. A first and second metal contact are applied to the semiconductor layers having the first and second type of conductivity, respectively, to complete the LED. The emission spectrum ranges from 190 nm to 369 nm. The illuminator may be configured in various materials, geometries, sizes and designs.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: April 15, 2014
    Assignee: Nitek, Inc.
    Inventors: Asif Khan, Vinod Adivarahan, Qhalid Fareed
  • Patent number: 8692293
    Abstract: Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: April 8, 2014
    Assignee: University of South Carolina
    Inventors: M. Asif Khan, Vinod Adivarahan, Qhalid Fareed, Grigory Simin, Naveen Tipimeni
  • Patent number: 8680551
    Abstract: A vertically conducting LED comprising, in a layered arrangement: a highly thermally conductive submount wherein the highly conductive submount has a thermal conductivity of at least 100 W/m0K; a p-type layer comprising Al1-x-yInyGax N wherein 0?x?1 and 0?y?1; a quantum well layer comprising Al1-x-yInyGaxN wherein 0?x?1 and 0?y?1; an n-type layer comprising Al1-x-yInyGaxN wherein 0?x?1 and 0?y?1; and an n-type contact layer wherein the LED has a peak emission at 200-365 nm.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: March 25, 2014
    Assignee: Nitek, Inc.
    Inventors: Vinod Adivarahan, Qhalid Fareed, Asif Khan
  • Publication number: 20140015011
    Abstract: Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).
    Type: Application
    Filed: July 2, 2013
    Publication date: January 16, 2014
    Inventors: M. Asif Khan, Vinod Adivarahan
  • Publication number: 20130313613
    Abstract: Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.
    Type: Application
    Filed: April 25, 2013
    Publication date: November 28, 2013
    Inventors: Asif Khan, Qhalid Fareed, Vinod Adivarahan