Patents by Inventor Vinod Adivarahan
Vinod Adivarahan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130313613Abstract: Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.Type: ApplicationFiled: April 25, 2013Publication date: November 28, 2013Inventors: Asif Khan, Qhalid Fareed, Vinod Adivarahan
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Publication number: 20130256631Abstract: Ultraviolet light emitting illuminator, and method for fabricating same, comprises an array of ultraviolet light emitting diodes and a first and second terminal. When an alternating current is applied across the first and second terminals and thus to each of the diodes, the illuminator emits ultraviolet light at a frequency corresponding to that of the alternating current. The illuminator includes a template with ultraviolet light emitting quantum wells, a first buffer layer with a first type of conductivity and a second buffer layer with a second type of conductivity, all deposited preferably over strain-relieving layer. A first and second metal contact are applied to the semiconductor layers having the first and second type of conductivity, respectively, to complete the LED. The emission spectrum ranges from 190 nm to 369 nm. The illuminator may be configured in various materials, geometries, sizes and designs.Type: ApplicationFiled: May 20, 2013Publication date: October 3, 2013Inventors: ASIF KHAN, VINOD ADIVARAHAN, QHALID FAREED
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Patent number: 8541817Abstract: An improved high breakdown voltage semiconductor device and method for manufacturing is provided. The device has a substrate and a AlaGa1-aN layer on the substrate wherein 0.1?a?1.00. A GaN layer is on the AlaGa1-aN layer. An In1-bGabN/GaN channel layer is on the GaN layer wherein 0.1?b?1.00. A AlcIndGa1-c-dN spacer layer is on the In1-bGabN/GaN layer wherein 0.1?c?1.00 and 0.0?d?0.99. A AleIn1-eN nested superlattice barrier layer is on the AlcIndGa1-c-dN spacer layer wherein 0.10?e?0.99. A AlfIngGa1-f-gN leakage suppression layer is on the AleIn1-eN barrier layer wherein 0.1?f?0.99 and 0.1?g?0.99 wherein the leakage suppression layer decreases leakage current and increases breakdown voltage during high voltage operation. A superstructure, preferably with metallic electrodes, is on the AlfIngGa1-f-gN leakage suppression layer.Type: GrantFiled: November 8, 2010Date of Patent: September 24, 2013Assignee: Nitek, Inc.Inventors: Qhalid Fareed, Vinod Adivarahan, Asif Khan
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Patent number: 8507941Abstract: Ultraviolet light emitting illuminator, and method for fabricating same, comprises an array of ultraviolet light emitting diodes and a first and a second terminal. When an alternating current is applied across the first and second terminals and thus to each of the diodes, the illuminator emits ultraviolet light at a frequency corresponding to that of the alternating current. The illuminator includes a template with ultraviolet light emitting quantum wells, a first buffer layer with a first type of conductivity and a second buffer layer with a second type of conductivity, all deposited preferably over a strain-relieving layer. A first and second metal contact are applied to the semiconductor layers having the first and second type of conductivity, respectively, to complete the LED. The emission spectrum ranges from 190 nm to 369 nm. The illuminator may be configured in various materials, geometries, sizes and designs.Type: GrantFiled: June 6, 2009Date of Patent: August 13, 2013Assignee: Nitek, Inc.Inventors: Asif Khan, Vinod Adivarahan, Qhalid Fareed
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Patent number: 8476125Abstract: Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).Type: GrantFiled: December 17, 2007Date of Patent: July 2, 2013Assignee: University of South CarolinaInventors: M. Asif Khan, Vinod Adivarahan
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Patent number: 8415654Abstract: A low resistance light emitting device with an ultraviolet light-emitting structure having a first layer with a first conductivity, a second layer with a second conductivity; and a light emitting quantum well region between the first layer and second layer. A first electrical contact is in electrical connection with the first layer and a second electrical contact is in electrical connection with the second layer. A template serves as a platform for the light-emitting structure. The ultraviolet light-emitting structure has a first layer having a first portion and a second portion of AlXInYGa(1-X-Y)N with an amount of elemental indium, the first portion surface being treated with silicon and indium containing precursor sources, and a second layer. When an electrical potential is applied to the first layer and the second layer the device emits ultraviolet light.Type: GrantFiled: March 27, 2009Date of Patent: April 9, 2013Assignee: Nitek, Inc.Inventors: Asif Khan, Qhalid Fareed, Vinod Adivarahan
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Patent number: 8372697Abstract: Novel silicon dioxide and silicon nitride deposition methods are generally disclosed. In one embodiment, the method includes depositing silicon on the surface of a substrate having a temperature of between about 65° C. and about 350° C. The heated substrate is exposed to a silicon source that is substantially free from an oxidizing agent. The silicon on the surface is then oxidized with an oxygen source that is substantially free from a silicon source. As a result of oxidizing the silicon, a silicon oxide layer forms on the surface of the substrate. Alternatively, or in additionally, a nitrogen source can be provided to produce silicon nitride on the surface of the substrate.Type: GrantFiled: May 7, 2007Date of Patent: February 12, 2013Assignee: University of South CarolinaInventors: Asif Khan, Vinod Adivarahan
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Publication number: 20130017689Abstract: Novel silicon dioxide and silicon nitride deposition methods are generally disclosed. In one embodiment, the method includes depositing silicon on the surface of a substrate having a temperature of between about 65° C. and about 350° C. The heated substrate is exposed to a silicon source that is substantially free from an oxidizing agent. The silicon on the surface is then oxidized with an oxygen source that is substantially free from a silicon source. As a result of oxidizing the silicon, a silicon oxide layer forms on the surface of the substrate. Alternatively, or in additionally, a nitrogen source can be provided to produce silicon nitride on the surface of the substrate.Type: ApplicationFiled: May 7, 2007Publication date: January 17, 2013Inventors: Asif Khan, Vinod Adivarahan
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Patent number: 8354663Abstract: An ultra-violet light-emitting diode (LED) array, 12, and method for fabricating same with an AlInGaN multiple-quantum-well active region, 500, exhibiting stable cw-powers. The LED includes a template, 10, with an ultraviolet light-emitting array structure on it. The template includes a first buffer layer, 321, then a second buffer layer, 421, on the first preferably with a strain-relieving layer in both buffer layers. Next there is a semiconductor layer having a first type of conductivity, 500, followed by a layer providing a quantum-well region, 600, with an emission spectrum ranging from 190 nm to 369 nm. Another semiconductor layer having a second type of conductivity is applied next, 800. A first metal contact, 980, is a charge spreading layer in electrical contact with the first layer and between the array of LED's. A second contact, 990, is applied to the semiconductor layer having the second type of conductivity, to complete the LED.Type: GrantFiled: August 13, 2008Date of Patent: January 15, 2013Assignee: Nitek, Inc.Inventors: Vinod Adivarahan, Asif Khan, Rubina Khan
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Patent number: 8354687Abstract: A high efficiency light emitting diode with an ultraviolet light-emitting structure. The structure has a first layer with a first conductivity comprising Al1-x-yInyGaxN wherein 0?x?1 and 0?y?1; a second layer with a second conductivity comprising Al1-x-yInyGaxN wherein 0?x?1 and 0?y?1; and a light emitting quantum well region between said first layer and said second layer comprising Al1-x-yInyGaxN wherein 0?x?1 and 0?y?1. The diode also has a carrier bonded to said first layer and said second layer wherein said carrier has a thermal conductivity of at least 100 W/mK and said carrier is resistive between a bonding location of said first layer and a second bonding location of said second layer.Type: GrantFiled: July 30, 2009Date of Patent: January 15, 2013Assignee: Nitek, Inc.Inventors: Vinod Adivarahan, Asif Khan, Qhalid Fareed
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Patent number: 8338273Abstract: An epitaxy procedure for growing extremely low defect density non-polar and semi-polar III-nitride layers over a base layer, and the resulting structures, is generally described. In particular, a pulsed selective area lateral overgrowth of a group III nitride layer can be achieved on a non-polar and semi-polar base layer. By utilizing the novel P-MOCVD or PALE and lateral over growth over selected area, very high lateral growth conditions can be achieved at relatively lower growth temperature which does not affect the III-N surfaces.Type: GrantFiled: December 17, 2007Date of Patent: December 25, 2012Assignee: University of South CarolinaInventors: M. Asif Khan, Vinod Adivarahan
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Patent number: 8318562Abstract: Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN.Type: GrantFiled: April 2, 2008Date of Patent: November 27, 2012Assignee: University of South CarolinaInventors: M. Asif Khan, Vinod Adivarahan, Qhalid Fareed, Grigory Simin, Naveen Tipirneni
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Publication number: 20120145994Abstract: An improved process for forming a UV emitting diode is described. The process includes providing a substrate. A super-lattice is formed directly on the substrate at a temperature of at least 800 to no more than 1,300° C. wherein the super-lattice comprises AlxInyGa1-x-yN wherein 0<x?1, 0?y?1 and 0<x+y?1. A first conductive layer with a first type of conductivity is formed on the super-lattice wherein the first conductive layer comprises AlxInyGa1-x-yN wherein 0<x?1, 0?y?1 and 0<x+y?1. A quantum well region is formed on the first conductive layer wherein the quantum well region comprises AlxInyGa1-x-yN wherein 0<x?1, 0?y?1 and 0<x+y?1. A second conductive layer is formed on the quantum well with a second type of conductivity wherein the second conductive layer comprises AlxInyGa1-x-yN wherein 0<x?1, 0?y?1 and 0<x+y?1.Type: ApplicationFiled: February 23, 2012Publication date: June 14, 2012Applicant: Nitek, IncInventors: Vinod ADIVARAHAN, Qhalid Fareed, Asif Khan
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Publication number: 20110108887Abstract: An improved high breakdown voltage semiconductor device and method for manufacturing is provided. The device has a substrate and a AlaGa1-aN layer on the substrate wherein 0.1?a?1.00. A GaN layer is on the AlaGa1-aN layer. An In1-bGabN/GaN channel layer is on the GaN layer wherein 0.1?b?1.00. A AlcIndGa1-c-dN spacer layer is on the In1-bGabN/GaN layer wherein 0.1?c?1.00 and 0.0?d?0.99. A AleIn1-eN nested superlattice barrier layer is on the AlcIndGa1-c-dN spacer layer wherein 0.10?e?0.99. A AlfIngGa1-f-gN leakage suppression layer is on the AleIn1-eN barrier layer wherein 0.1?f?0.99 and 0.1?g?0.99 wherein the leakage suppression layer decreases leakage current and increases breakdown voltage during high voltage operation. A superstructure, preferably with metallic electrodes, is on the AlfIngGa1-f-gN leakage suppression layer.Type: ApplicationFiled: November 8, 2010Publication date: May 12, 2011Inventors: Qhalid Fareed, Vinod Adivarahan, Asif Khan
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Publication number: 20110073838Abstract: Ultraviolet light emitting illuminator, and method for fabricating same, comprises an array of ultraviolet light emitting diodes and a first and a second terminal. When an alternating current is applied across the first and second terminals and thus to each of the diodes, the illuminator emits ultraviolet light at a frequency corresponding to that of the alternating current. The illuminator includes a template with ultraviolet light emitting quantum wells, a first buffer layer with a first type of conductivity and a second buffer layer with a second type of conductivity, all deposited preferably over a strain-relieving layer. A first and second metal contact are applied to the semiconductor layers having the first and second type of conductivity, respectively, to complete the LED. The emission spectrum ranges from 190 nm to 369 nm. The illuminator may be configured in various materials, geometries, sizes and designs.Type: ApplicationFiled: June 6, 2009Publication date: March 31, 2011Inventors: Asif Khan, Vinod Adivarahan, Qhalid Fareed
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Publication number: 20110012089Abstract: A low resistance light emitting device with an ultraviolet light-emitting structure having a first layer with a first conductivity, a second layer with a second conductivity; and a light emitting quantum well region between the first layer and second layer. A first electrical contact is in electrical connection with the first layer and a second electrical contact is in electrical connection with the second layer. A template serves as a platform for the light-emitting structure. The ultraviolet light-emitting structure has a first layer having a first portion and a second portion of AlXInYGa(1-X-Y)N with an amount of elemental indium, the first portion surface being treated with silicon and indium containing precursor sources, and a second layer. When an electrical potential is applied to the first layer and the second layer the device emits ultraviolet light.Type: ApplicationFiled: March 27, 2009Publication date: January 20, 2011Inventors: Asif Khan, Qhalid Fareed, Vinod Adivarahan
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Publication number: 20100264401Abstract: An ultra-violet light-emitting diode (LED) array, 12, and method for fabricating same with an AlInGaN multiple-quantum-well active region, 500, exhibiting stable cw-powers. The LED includes a template, 10, with an ultraviolet light-emitting array structure on it. The template includes a first buffer layer, 321, then a second buffer layer, 421, on the first preferably with a strain-relieving layer in both buffer layers. Next there is a semiconductor layer having a first type of conductivity, 500, followed by a layer providing a quantum-well region, 600, with an emission spectrum ranging from 190 nm to 369 nm. Another semiconductor layer having a second type of conductivity is applied next, 800. A first metal contact, 980, is a charge spreading layer in electrical contact with the first layer and between the array of LED's. A second contact, 990, is applied to the semiconductor layer having the second type of conductivity, to complete the LED.Type: ApplicationFiled: August 13, 2008Publication date: October 21, 2010Inventors: Vinod Adivarahan, Asif Khan, Rubina Khan
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Publication number: 20100187545Abstract: The present invention is generally directed to methods of selectively doping a substrate and the resulting selectively doped substrates. The methods include doping an epilayer of a substrate with the selected doping material to adjust the conductivity of either the epilayers grown over a substrate or the substrate itself. The methods utilize lithography to control the location of the doped regions on the substrate. The process steps can be repeated to form a cyclic method of selectively doping different areas of the substrate with the same or different doping materials to further adjust the properties of the resulting substrate.Type: ApplicationFiled: November 13, 2007Publication date: July 29, 2010Applicant: UNIVERSITY OF SOUTH CAROLINAInventors: Asif Khan, Vinod Adivarahan
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Publication number: 20100140745Abstract: An epitaxy procedure for growing extremely low defect density non-polar and semi-polar III-nitride layers over a base layer, and the resulting structures, is generally described. In particular, a pulsed selective area lateral overgrowth of a group III nitride layer can be achieved on a non-polar and semi-polar base layer. By utilizing the novel P-MOCVD or PALE and lateral over growth over selected area, very high lateral growth conditions can be achieved at relatively lower growth temperature which does not affect the III-N surfaces.Type: ApplicationFiled: December 17, 2007Publication date: June 10, 2010Inventors: M. Asif Khan, Vinod Adivarahan
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Publication number: 20100102359Abstract: Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).Type: ApplicationFiled: December 17, 2007Publication date: April 29, 2010Applicant: UNIVERSITY OF SOUTH CAROLINAInventors: M. Asif Khan, Vinod Adivarahan