Patents by Inventor Vinod Menezes
Vinod Menezes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9734896Abstract: In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines.Type: GrantFiled: June 30, 2016Date of Patent: August 15, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Per Torstein Roine, Vinod Menezes, Mahesh Mehendale, Vamsi Gullapalli, Premkumar Seetharaman
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Patent number: 9698770Abstract: A low power reset circuit includes a bias generator for receiving an operating voltage generated by a power supply and generating a bias voltage in response to the received operating voltage. The operation speed of a shaper for generating a shaped signal for indicating the operating voltage and the operation speed of a comparator for comparing a threshold reference voltage with the shaped signal are both controlled in response to the generated bias voltage. The comparator also generates a comparison signal for indicating a result of the comparison. In response to the comparison signal, a reset signal generator generates a reset signal for resetting protected circuitry powered by the operating voltage generated by the power supply.Type: GrantFiled: April 7, 2016Date of Patent: July 4, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Vinod Menezes
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Publication number: 20170154672Abstract: A static random access memory (SRAM) includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns. The rows correspond to word lines and the columns correspond to bit lines. The first sense amplifier includes a first transistor and a second transistor. The first sense amplifier is configured to provide a first read of a first storage cell of the array of storage cells. Based on the first read of the first storage cell failing to correctly read data stored in the first storage cell, the first sense amplifier is configured to increment a body bias of the first transistor a first time. In response to the body bias of the first transistor being incremented, the first sense amplifier is configured to provide a second read of the first storage cell.Type: ApplicationFiled: November 30, 2015Publication date: June 1, 2017Inventor: Vinod MENEZES
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Publication number: 20170153288Abstract: A method of testing a semiconductor wafer comprising a scribe line and a plurality of dies. The method includes implementing a first landing pad on the scribe line and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the plurality of dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip and applying an ATE resource to the first cluster of dies.Type: ApplicationFiled: April 15, 2016Publication date: June 1, 2017Inventors: Rubin Ajit PAREKHJI, Mahesh M. MEHENDALE, Vinod MENEZES, Vipul K. SINGHAL
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Publication number: 20170101284Abstract: A printing system includes at least one main printer arranged to print images onto main sequence sheets that are passed sequentially through the main printer; an inserter arranged to insert individual sheets as insert sheets into a stream of main sequence sheets that have left the main printer, thereby to form a mixed sheet sequence; and a conveyer arranged to convey the sheets of the mixed sheet sequence one by one towards an output unit. An insert sheet printer is connected to the inserter for printing the insert sheets and forwarding them to the inserter.Type: ApplicationFiled: October 7, 2015Publication date: April 13, 2017Applicant: OCÉ-TECHNOLOGIES B.V.Inventor: Vinod MENEZES
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Patent number: 9613685Abstract: A static random access memory (SRAM) includes an array of storage cells arranged as rows and columns and a read controller to manage reading from the storage cells. The array of storage cells includes word lines that correspond to the rows and bit lines that correspond to the columns. The read controller is configured to receive a precharge signal and a word line signal and identify consecutive reads from storage cells accessed via a same one of the word lines. The read controller is further configured to, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in a partial burst mode, precharge the bit lines no more than once during the consecutive reads and charge the same one of the word lines after each read of the consecutive reads.Type: GrantFiled: November 13, 2015Date of Patent: April 4, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Premkumar Seetharaman, Vinod Menezes
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Patent number: 9571104Abstract: Methods and apparatus permit body biasing to be controlled for transistors of a logic device. By controlling the body biasing, transistor threshold voltages can be controlled—increased during standby modes of the logic device to reduce leakage current and decreased during active modes and to increase switching speed during the active modes. The change in the body biasing can be made relatively slowly to reduce wasted energy that would otherwise be dissipated as heat. In a method embodiment, the method includes obtaining first and second body bias slope parameters, each slope parameter defining, at least in part, a slope of a body bias voltage signal. The method includes charging a body of a transistor with a bias voltage signal per the first body bias slope parameter to lower a threshold voltage, and discharging the body per the second body bias slope parameter to decrease leakage current of the transistor.Type: GrantFiled: October 19, 2015Date of Patent: February 14, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Vinod Menezes
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Publication number: 20170025167Abstract: A static random access memory (SRAM) features reduced write cycle power consumption. The SRAM includes an array of static storage cells and a write controller. The array of static storage cells is accessible via a plurality of word lines and a plurality of bit lines, and is arranged to access multiple bits via each of the word lines. The write controller controls writing to the static storage cells. The write controller is configured to perform consecutive writes to a plurality of addresses associated with a same one of the word lines, and to, in conjunction with the consecutive writes, perform fewer precharges of the bit lines than consecutive writes.Type: ApplicationFiled: October 4, 2016Publication date: January 26, 2017Inventor: Vinod Menezes
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Publication number: 20160314832Abstract: In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines.Type: ApplicationFiled: June 30, 2016Publication date: October 27, 2016Inventors: Per Torstein Roine, Vinod Menezes, Mahesh Mehendale, Vamsi Gullapalli, Premkumar Seetharaman
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Patent number: 9384826Abstract: In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.Type: GrantFiled: December 5, 2014Date of Patent: July 5, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Per Torstein Roine, Vinod Menezes, Mahesh Mehendale, Vamsi Gullapalli, Premkumar Seetharaman
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Publication number: 20160163379Abstract: In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.Type: ApplicationFiled: December 5, 2014Publication date: June 9, 2016Inventors: Per Torstein Roine, Vinod Menezes, Mahesh Mehendale, Vamsi Gullapalli, Premkumar Seetharaman
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Publication number: 20160071577Abstract: A static random access memory (SRAM) features reduced write cycle power consumption. The SRAM includes an array of static storage cells and a write controller. The array of static storage cells is accessible via a plurality of word lines and a plurality of bit lines, and is arranged to access multiple bits via each of the word lines. The write controller controls writing to the static storage cells. The write controller is configured to perform consecutive writes to a plurality of addresses associated with a same one of the word lines, and to, in conjunction with the consecutive writes, perform fewer precharges of the bit lines than consecutive writes.Type: ApplicationFiled: September 8, 2015Publication date: March 10, 2016Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Vinod MENEZES
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Publication number: 20160064070Abstract: A static random access memory (SRAM) that includes an array of storage cells arranged as rows and columns and a read controller to manage reading from the storage cells. The array of storage cells includes word lines that correspond to the rows and bit lines that correspond to the columns. The read controller is configured to identify consecutive reads from storage cells accessed via a same one of the word lines and precharge the bit lines no more than once during the consecutive reads.Type: ApplicationFiled: September 2, 2015Publication date: March 3, 2016Inventors: Vinod MENEZES, Premkumar SEETHARAMAN
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Publication number: 20160064069Abstract: In some embodiments, an SRAM includes an array of storage cells arranged as rows and columns, each storage cell of the array of storage cells includes a first type of transistor and a second type of transistor. The SRAM also includes a memory controller configured to detect a temperature of the SRAM and apply a body bias to the first type of transistor in each of the storage cells and refrain from an application of a body bias to the second type of transistor in each of the storage cells.Type: ApplicationFiled: September 2, 2015Publication date: March 3, 2016Inventors: Vinod MENEZES, Premkumar SEETHARAMAN
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Patent number: 8812885Abstract: A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.Type: GrantFiled: April 2, 2007Date of Patent: August 19, 2014Assignee: Texas Instruments IncorporatedInventors: Philippe Royannez, Gilles Dubost, Christophe Vatinel, William Douglas Wilson, Vinod Menezes, Hugh Mair, James Sangwon Song
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Patent number: 8379465Abstract: Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode and with write assist bias in a normal operating mode. The memory is constructed of multiple memory array blocks of SRAM cells. Bias devices are associated with each memory array block, and associated with one or more columns. Each bias device includes a diode-connected transistor in parallel with a shorting transistor, between a power supply voltage and a power supply bias node for cells in its column or columns. The shorting transistor receives control signals from control logic so that the diode-connected transistor for each column is shorted during read cycles, and in write cycles in which its columns are not selected; in write cycles in which its columns are selected, the shorting transistor in the bias device is turned off, so that a reduced power supply voltage is applied to the selected column. The shorting transistors for all columns in the block are turned off in the RTA mode.Type: GrantFiled: April 21, 2010Date of Patent: February 19, 2013Assignee: Texas Instruments IncorporatedInventors: Michael Patrick Clinton, Lakshmikantha V. Holla, Vinod Menezes
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Publication number: 20120266123Abstract: Coherent analysis of asymmetric aging and statistical process variation. A method of designing a circuit includes preparing an initial netlist of components in the circuit. A plurality of components is selected from the initial netlist by a first statistical process. Further, a process variation netlist is prepared by replacing a plurality of initial operating parameters of the plurality of components with a plurality of process variation operating parameters. A plurality of high stress components is then identified in the process variation netlist and an aged netlist is prepared by replacing a set of operating parameters of the plurality of high stress components with a set of degraded operating parameters. The circuit is simulated using the aged netlist. The method also includes modifying the initial netlist according to a result of simulation and repeating the foregoing steps until a desired circuit performance is obtained.Type: ApplicationFiled: April 12, 2011Publication date: October 18, 2012Applicant: Texas Instruments IncorporatedInventors: Palkesh JAIN, Vinod Menezes, Francisco Cano
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Publication number: 20110261632Abstract: Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode and with write assist bias in a normal operating mode. The memory is constructed of multiple memory array blocks of SRAM cells. Bias devices are associated with each memory array block, and associated with one or more columns. Each bias device includes a diode-connected transistor in parallel with a shorting transistor, between a power supply voltage and a power supply bias node for cells in its column or columns. The shorting transistor receives control signals from control logic so that the diode-connected transistor for each column is shorted during read cycles, and in write cycles in which its columns are not selected; in write cycles in which its columns are selected, the shorting transistor in the bias device is turned off, so that a reduced power supply voltage is applied to the selected column. The shorting transistors for all columns in the block are turned off in the RTA mode.Type: ApplicationFiled: April 21, 2010Publication date: October 27, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael Patrick Clinton, Lakshmikantha V. Holla, Vinod Menezes
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Publication number: 20100007374Abstract: The method, system, and apparatus of on-die Thevenin termination for high speed I/O interface are disclosed. In one embodiment, a system of terminating a transmission line of a chip includes a pull-up circuit located within the chip comprising a voltage source and a positive switch device coupled with the transmission line of the chip, a pull-down circuit located within the chip comprising a ground and a negative switch device coupled with the transmission line of the chip, a resistor located within the chip coupled with the voltage source, the positive switch device, the ground, the negative switch device, and a pad coupled with the resistor to terminate the transmission line of the chip. The system may include resistors coupled in parallel with each other. The system may include an impedance module to determine a load impedance value as seen from the pad that matches a source impedance value.Type: ApplicationFiled: July 14, 2008Publication date: January 14, 2010Inventors: Rajat Chauhan, Karthik Rajagopal, Vinod Menezes
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Publication number: 20080162969Abstract: A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.Type: ApplicationFiled: April 2, 2007Publication date: July 3, 2008Applicant: Texas Instruments IncorporatedInventors: Philippe Royannez, Gilles Dubost, Christophe Vantinel, William Douglas Wilson, Vinod Menezes, Hugh Mair, James Sangwon Song