Abstract: Suspended charge storage regions are utilized for non-volatile storage to decrease parasitic interferences and increase charge retention in memory devices. Charge storage regions are suspended from an overlying intermediate dielectric material. The charge storage regions include an upper surface and a lower surface that extend in the row and column directions. The upper surface of the charge storage region is coupled to the overlying intermediate dielectric material. The lower surface faces the substrate surface and is separated from the substrate surface by a void. The charge storage region includes a first vertical sidewall and a second vertical sidewall that extend in the column direction and a third vertical sidewall and fourth vertical sidewall that extend in the row direction. The first, second, third, and fourth vertical sidewall are separated from neighboring features of the non-volatile memory by the void. The void may include a vacuum, air, gas, or a liquid.

Abstract: A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer.

Abstract: Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices.

Abstract: Methods of forming single crystal channel material in a 3-d flash memory cell using only gas-phase etching techniques are described. The methods include gas-phase etching native oxide from a polysilicon layer on a conformal ONO layer. The gas-phase etch also removes native oxide from the exposed single crystal silicon substrate the bottom of a 3-d flash memory hole. The polysilicon layer is removed, also with a gas-phase etch, on the same substrate processing mainframe. Both native oxide removal and polysilicon removal use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. Epitaxial silicon is then grown from the exposed single crystal silicon to create a high mobility replacement channel.

Abstract: Methods of forming air gaps in a 3-d flash memory cell using only gas-phase etching techniques are described. The methods include selectively gas-phase etching tungsten deposited into the stack structure to separate the tungsten levels. Other metals than tungsten may be used. The methods also include selectively etching silicon oxide from between the tungsten levels to make room for vertically spaced air gaps. A nonconformal silicon oxide layer is then deposited to trap the air gaps. Both tungsten removal and silicon oxide removal use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. The nonconformal silicon oxide may be deposited inside or outside the mainframe.

Abstract: Methods of etching back shallow trench isolation (STI) dielectric and trimming the exposed floating gate without breaking vacuum are described. The methods include recessing silicon oxide dielectric gapfill to expose vertical sidewalls of polysilicon floating gates. The exposed vertical sidewalls are then isotropically etched to evenly thin the polysilicon floating gates on the same substrate processing mainframe. Both recessing silicon oxide and isotropically etching polysilicon use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. An inter-poly dielectric may then be conformally deposited either on the same mainframe or outside the mainframe.

Abstract: Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.

Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.

Abstract: A non-volatile memory system, comprising non-volatile storage device with word lines having an inverted T-shape over floating gates. The inverted T-shape shape has a wider bottom portion and a thinner top portion. The thinner top portion increases the separation between adjacent word lines relative to the separation between the wider bottom portions. An air gap may separate adjacent word lines. The thinner top portion of the word lines increases the path length between adjacent word lines. The likelihood of word line to word line short may be decreased by reducing the electric field between adjacent word lines.

Abstract: A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer. The raised structures can be independent or joined to one another at a bottom of the bottom electrode layer. A resistance-switching material is provided between and above the bottom electrode structure, followed by a top electrode layer. Or, insulation is provided between and above the bottom electrode structures, and the resistance-switching material and top electrode layer are above the insulation. Less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more raised structures. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Abstract: An embodiment relates to a memory device that includes a semiconductor channel, a tunnel dielectric located over the semiconductor channel, a charge storage region located over the tunnel dielectric, a blocking dielectric located over the charge storage region, and a control gate located over the blocking dielectric. An interface between the blocking dielectric and the control gate substantially prevents oxygen diffusion from the blocking dielectric into the control gate.

Abstract: Methods of etching back an oxide-nitride-oxide (ONO) layer of a 3-d flash memory cell without breaking vacuum are described. The methods include recessing the two outer silicon oxide dielectric layers to expose the flanks of the thin silicon nitride layer. The silicon nitride layer is then etched back from all exposed sides to hasten the process on the same substrate processing mainframe. Both etching back the silicon oxide and etching back the silicon nitride use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. The process may also be reversed such that the silicon nitride is etched back first.

Abstract: Methods are described for forming “air gaps” between adjacent copper lines on patterned substrates. The air gaps may be located between copper lines on the same layer. A sacrificial patterned dielectric layer is used as a template to form a layer of copper by physical vapor deposition in a substrate processing system (i.e. a mainframe). Without breaking vacuum, the copper is redistributed into the gaps with a copper reflow process. Dielectric material from the template is removed, again in the same mainframe, using a remote fluorine etch process leaving the gapfill copper as the structural material. A conformal capping layer (such as silicon carbon nitride) is then deposited (e.g. by ALD) to seal the patterned substrate before removing the patterned substrate from the mainframe.

Abstract: Flash memory cells and methods of formation are described for flash memory cells having air gaps through which electrons may pass to alter the charge state of the floating gate. A dummy gate is initially deposited and a polysilicon gate is deposited on the dummy gate. A silicon oxide film is then deposited on the sides of the active area, the dummy gate and the polysilicon. The silicon oxide film holds the polysilicon in place while the dummy gate is selectively etched away. The dummy gate may be doped to increase etch rate. Formerly, silicon oxide was used as a dielectric barrier through which electrons were passed to charge and discharge the floating gate (polysilicon). Eliminating material in the dielectric barrier reduces the tendency to accumulate trapped charges during use and increase the lifespan of flash memory devices.

Abstract: Flash memory cells and methods of formation are described for flash memory cells having air gaps through which electrons may pass to alter the charge state of the floating gate. A dummy gate is initially deposited and a polysilicon gate is deposited on the dummy gate. A silicon oxide film is then deposited on the sides of the active area, the dummy gate and the polysilicon. The silicon oxide film holds the polysilicon in place while the dummy gate is selectively etched away. The dummy gate may be doped to increase etch rate. Formerly, silicon oxide was used as a dielectric barrier through which electrons were passed to charge and discharge the floating gate (polysilicon). Eliminating material in the dielectric barrier reduces the tendency to accumulate trapped charges during use and increase the lifespan of flash memory devices.

Abstract: Air gaps are provided to reduce interference and resistance between metal bit lines in non-volatile memory structures. Metal vias can be formed that are electrically coupled with the drain region of an underlying device and extend vertically with respect to the substrate surface to provide contacts for bit lines that are elongated in a column direction above. The metal vias can be separated by a dielectric fill material. Layer stack columns extend in a column direction over the dielectric fill and metal vias. Each layer stack column includes a metal bit line over a nucleation line. Each metal via contacts one of the layer stack columns at its nucleation line. A low temperature dielectric liner extends along sidewalls of the layer stack columns. A non-conformal dielectric overlies the layer stack columns defining a plurality of air gaps between the layer stack columns.

Abstract: A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer. The raised structures can be independent or joined to one another at a bottom of the bottom electrode layer. A resistance-switching material is provided between and above the bottom electrode structure, followed by a top electrode layer. Or, insulation is provided between and above the bottom electrode structures, and the resistance-switching material and top electrode layer are above the insulation. Less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more raised structures. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Abstract: Suspended charge storage regions are utilized for non-volatile storage to decrease parasitic interferences and increase charge retention in memory devices. Charge storage regions are suspended from an overlying intermediate dielectric material. The charge storage regions include an upper surface and a lower surface that extend in the row and column directions. The upper surface of the charge storage region is coupled to the overlying intermediate dielectric material. The lower surface faces the substrate surface and is separated from the substrate surface by a void. The charge storage region includes a first vertical sidewall and a second vertical sidewall that extend in the column direction and a third vertical sidewall and fourth vertical sidewall that extend in the row direction. The first, second, third, and fourth vertical sidewall are separated from neighboring features of the non-volatile memory by the void. The void may include a vacuum, air, gas, or a liquid.

Abstract: Methods are described for forming “air gaps” between adjacent copper lines on patterned substrates. The common name “air gap” will be used interchangeably the more technically accurate “gas pocket” and both reflect a variety of pressures and elemental ratios. The gas pockets may be one or more pores within dielectric material located between copper lines. Adjacent copper lines may be bordered by a lining layer and air gaps may extend from one lining layer on one copper line to the lining layer of an adjacent copper line. The gas pockets can have a dielectric constant approaching one, favorably reducing interconnect capacitance compared with typical low-K dielectric materials.

Abstract: Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices.