Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Abstract: Methods and apparatuses relating to offload operations are described. In one embodiment, a hardware processor includes a core to execute a thread and offload an operation; and a first and second hardware accelerator to execute the operation, wherein the first and second hardware accelerator are coupled to shared buffers to store output data from the first hardware accelerator and provide the output data as input data to the second hardware accelerator, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator with a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator with an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator with a corresponding response entry for each respective shared buffer.

Abstract: Instruction sets for variable length integer (varint) coding and associated methods and apparatus. The instructions sets include instructions for encoding and decoding varints, and may be included as a part of an instruction set architecture (ISA) for processors architectures such as x86 and Arm-based architectures, as well as other ISAs. In one aspect, the instructions include, a varint size encode instruction to encode a size of a varint, a varint encode instruction to encode a varint, a varint size decode instruction to decode a size of an encoded varint, and a varint decode instruction to decode an encoded varint. Varint encode size and encode instructions may be combined in a single instructions. Similarly, varint decode size and decode instructions may be combined in a single instruction. In one aspect, the instructions use a variable-length quantity (VLQ) encoding scheme under which varints are encoded into one or more VLQ octets.

Abstract: A storage device is described. The storage device includes non volatile memory having data storage resources organized into slots to store chunks of data. The storage device includes memory to store a data pointer table having groups of pointers to the slots. Each of the groups correspond to a respective block that is stored in the non volatile memory. Certain ones of the pointers are to have an associated set of hashes of different segments of the respective chunks that are pointed to by the certain ones of the pointers. The storage device includes a search module to implement a search function within the storage device that hashes a search key and compares the hashed search key to the hashes of the different segments to identify a possible match to the search key.

Abstract: Technologies for high-performance single-stream data compression include a computing device that updates an index data structure based on an input data stream. The input data stream is divided into multiple chunks. Each chunk has a predetermined length, such as 136 bytes, and overlaps the previous chunk by a predetermine amount, such as eight bytes. The computing device processes multiple chunks in parallel using the index data to generate multiple token streams. The tokens include literal tokens and reference tokens that refer to matching data from earlier in the input data stream. The computing device thus searches for matching data in parallel. The computing device merges the token streams to generate a single output token stream. The computing device may merge a pair of tokens from two different chunks to generate one or more synchronized tokens that are output to the output token stream. Other embodiments are described and claimed.

Abstract: Techniques and apparatus for verification of compressed data are described. In one embodiment, for example an apparatus to provide verification of compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access compressed data, access compression information associated with the compressed data, decompress at least a portion of the compressed data to generate decompressed data, and verify the compressed data via a comparison of the decompressed data with the compression information. Other embodiments are described and claimed.

Abstract: A processor includes a decoder to decode an instruction to compress an input data stream and an execution unit for executing the instruction. The execution unit to generate metadata for a current input of the input data stream, the metadata comprises a first hint based on a portion of a current input that represents the input data stream at a current offset, select a first pointer to identify a location in a history buffer in a hash chain, determine whether the metadata generated for the current input matches metadata previously generated for the first pointer, and filter the first pointer from a search for a best match for the current input in the history buffer based on the determination that at least a portion of the metadata for the current input does not match a portion of the metadata for the first pointer.

Abstract: Technologies for data decompression include a computing device that reads a symbol tag byte from an input stream. The computing device determines whether the symbol can be decoded using a fast-path routine, and if not, executes a slow-path routine to decompress the symbol. The slow-path routine may include data-dependent branch instructions that may be unpredictable using branch prediction hardware. For the fast-path routine, the computing device determines a next symbol increment value, a literal increment value, a data length, and an offset based on the tag byte, without executing an unpredictable branch instruction. The computing device sets a source pointer to either literal data or reference data as a function of the tag byte, without executing an unpredictable branch instruction. The computing device may set the source pointer using a conditional move instruction. The computing device copies the data and processes remaining symbols. Other embodiments are described and claimed.

Abstract: One embodiment provides an apparatus. The apparatus includes a single instruction multiple data (SIMD) hash module configured to apportion at least a first portion of a message of length L to a number (S) of segments, the message including a plurality of sequences of data elements, each sequence including S data elements, a respective data element in each sequence apportioned to a respective segment, each segment including a number N of blocks of data elements and to hash the S segments in parallel, resulting in S segment digests, the S hash digests based, at least in part, on an initial value and to store the S hash digests; a padding module configured to pad a remainder, the remainder corresponding to a second portion of the message, the second portion related to the length L of the message, the number of segments and a block size; and a non-SIMD hash module configured to hash the padded remainder, resulting in an additional hash digest and to store the additional hash digest.

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Abstract: Provided are a memory system, memory controller, and method for using a memory address to form a tweak key to use to encrypt and decrypt data. A base tweak co is generated as a function of an address of a block of data in the memory storage. For each sub-block of the block, performing: processing the base tweak to determine a sub-block tweak; combining the sub-block tweak with the sub-block to produce a modified sub-block; and performing an encryption operation comprising one of encryption or decryption on the modified sub-block to produce sub-block output comprising one of encrypted data and unencrypted data for the sub-block.

Abstract: An apparatus and method are described for executing hash functions on a processor.

Abstract: Memory compression devices, systems, and associated methods are provided and described. Such devices, systems, and methods increase the effective bandwidth and reduce power consumption of non-volatile memory subsystems.

Abstract: A processor of an aspect includes a decode unit to decode an elliptic curve cryptography (ECC) point-multiplication with obfuscated input information instruction. The ECC point-multiplication with obfuscated input information instruction is to indicate a plurality of source operands that are to store input information for an ECC point-multiplication operation. At least some of the input information that is to be stored in the plurality of source operands is to be obfuscated. An execution unit is coupled with the decode unit. The execution unit, in response to the ECC point-multiplication with obfuscated input information instruction, is to store an ECC point-multiplication result in a destination storage location that is to be indicated by the ECC point-multiplication with obfuscated input information instruction. Other processors, methods, systems, and instructions are disclosed.

Abstract: Methods and apparatus for a secure memory controller. The secure memory controller includes circuitry and logic that is programmed to prevent malicious code from overwrite protected regions of system memory. The memory controller observes memory access patterns and trains itself to identify thread stacks and addresses relating to the thread stacks including stack-frame pointers and return addresses. In one aspect, the memory controller prevents a return address from being overwritten until a proper return from a function call is detected. The memory controller is also configured to prevent malicious code from overwriting page table entries (PTEs) in page tables. Pages containing PTEs are identified, and access is prevented to the PTEs from user-mode code. The PTEs are also scanned to detect corrupted PTEs resulting from bit manipulation by malicious code.

Abstract: In one embodiment, an apparatus comprises a processor to receive a plurality of values of a data set, the data set comprising a first value, a second value, and a third value; calculate and store a first delta corresponding to the first value, wherein the first delta is equal to the difference between the first value and the second value; and calculate and store a second delta corresponding to the second value, wherein the second delta is equal to the difference between the second value and the third value.

Abstract: Vector instructions for performing ZUC stream cipher operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first vector instruction to perform an update to a liner feedback shift register (LFSR), and receives a second vector instruction to perform an update to a state of a finite state machine (FSM), where the FSM receives inputs from re-ordered bits of the LFSR. The execution circuitry executes the first vector instruction and the second vector instruction in a single-instruction multiple data (SIMD) pipeline.

Abstract: Vector instructions for performing SNOW 3G wireless security operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first operand of the first instruction specifying a first vector register that stores a current state of a finite state machine (FSM). The execution circuitry also receives a second operand of the first instruction specifying a second vector register that stores data elements of a liner feedback shift register (LFSR) that are needed for updating the FSM. The execution circuitry executes the first instruction to produce a updated state of the FSM and an output of the FSM in a destination operand of the first instruction.

Abstract: Technologies for heuristic Huffman code generation include a computing device that generates a weighted list of symbols for a data block. The computing device determines a threshold weight and identifies one or more lightweight symbols in the list that have a weight less than or equal to the threshold weight. The threshold weight may be the average weight of all symbols with non-zero weight in the list. The computing device generates a balanced sub-tree of nodes for the lightweight symbols, with each lightweight symbol associated with a leaf node. The computing device adds the remaining symbols and the root of the balanced sub-tree to a heap and generates a Huffman code tree by processing the heap. The threshold weight may be adjusted to tune performance and compression ratio. Other embodiments are described and claimed.

Abstract: Technologies for compressing data with multiple hash tables include a compute device. The compute device is to produce, for each of multiple string prefixes of different string prefix sizes, an associated hash. Each string prefix defines a set of consecutive symbols in a string that starts at a present position in an input stream of symbols. The compute device is also to write, to a different hash table for each string prefix size, a pointer to the present position in association with the associated hash. Each hash is usable as an index into the associated hash table to provide the present position of the string.