Patents by Inventor Vipin Tiwari

Vipin Tiwari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220254414
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. In one example, a method for programming a plurality of non-volatile memory cells in an array of non-volatile memory cells, comprises generating a high voltage, and programming a plurality of non-volatile memory cells in an array using the high voltage when a programming enable signal is asserted and providing a feedback loop to maintain the high voltage while programming the plurality of non-volatile memory cells.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 11, 2022
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Patent number: 11409352
    Abstract: Numerous embodiments of power management techniques are disclosed for various operations involving one or more vector-by-matrix multiplication (VMM) arrays within an artificial neural network.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: August 9, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
  • Patent number: 11393546
    Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: July 19, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
  • Patent number: 11393535
    Abstract: Embodiments for ultra-precise tuning of a selected memory cell are disclosed. The selected memory cell optionally is first programmed using coarse programming and fine programming methods. The selected memory cell then undergoes ultra-precise programming through the programming of an adjacent memory cell. As the adjacent memory cell is programmed, capacitive coupling between the floating gate of the adjacent memory cell and the floating gate of the selected memory cell will cause the voltage of the floating gate of the selected memory cell to increase, but in smaller increments than could be achieved by programming the selected memory cell directly. In this manner, the selected memory cell can be programmed with ultra-precise gradations.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: July 19, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Steven Lemke, Hieu Van Tran, Yuri Tkachev, Louisa Schneider, Henry A. Om'Mani, Thuan Vu, Nhan Do, Vipin Tiwari
  • Patent number: 11373707
    Abstract: A non-volatile memory device is disclosed. The non-volatile memory device comprises an array of flash memory cells comprising a plurality of flash memory cells organized into rows and columns, wherein the array is further organized into a plurality of sectors, each sector comprising a plurality of rows of flash memory cells, and a row driver selectively coupled to a first row and a second row.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 28, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Vipin Tiwari, Nhan Do
  • Patent number: 11355184
    Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: June 7, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Vipin Tiwari
  • Publication number: 20220147794
    Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 12, 2022
    Inventors: FARNOOD MERRIKH BAYAT, XINJIE GUO, DMITRI STRUKOV, NHAN DO, HIEU VAN TRAN, VIPIN TIWARI, MARK REITEN
  • Publication number: 20220130477
    Abstract: The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. The embodiments comprise a system and method for receiving an erase command and a logical address, the logical address corresponding to a sector of physical words of non-volatile memory cells in an array of non-volatile memory cells, the sector comprising a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word; when a current word, identified by an index bit, is the last physical word in the sector, erasing the sector; and when the current word is not the last physical word in the sector, changing a next index bit.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Inventors: Guangming Lin, Xiaozhou Qian, Xiao Yan Pl, Vipin Tiwari, Zhenlin Ding
  • Patent number: 11308383
    Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: April 19, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten
  • Publication number: 20220092878
    Abstract: The disclosure provides a method for document management in a network. The method includes acquiring, by an electronic device, a source document as an image, extracting, by the electronic device, a plurality of multi-modal information from the source document by parsing the source document, automatically determining, by the electronic device, a category of the source document based on a comparison of the extracted plurality of multi-modal information with a plurality of pre-defined features, extracting, by the electronic device, a plurality of data fields corresponding to the determined category from the source document, determining, by the electronic device, a priority for each of the plurality of data fields and storing, by the electronic device, the plurality of data fields in at least one of a secure information source and an unsecure information source based on the determined priority.
    Type: Application
    Filed: January 2, 2020
    Publication date: March 24, 2022
    Inventors: Bokul BORAH, Prachi GUPTA, Shalab SHALAB, Ayushi GUPTA, Theophilus THOMAS, Sumit Kumar TIWARY, Bindu Madhavi MISHRA, Dalbir Singh DHILLON, Manoj KUMAR, Santosh Pallav SAHU, Shweta GARG, Sourav CHATTERJEE, Tasleem ARIF, Naresh Kumar GUPTA, Pooja PAWWAR, Vipin TIWARI
  • Patent number: 11270763
    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: March 8, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Patent number: 11270771
    Abstract: A neural network device with synapses having memory cells each having source and drain regions in a semiconductor substrate with a channel region extending there between, a floating gate over an entirety of the channel region, and a first gate over the floating gate. First lines each electrically connect together the first gates in one of the memory cell rows, second lines each electrically connect together the source regions in one of the memory cell rows, and third lines each electrically connect together the drain regions in one of the memory cell columns. The synapses are configured to receive a first plurality of inputs as electrical voltages on the first lines or on the second lines, and to provide a first plurality of outputs as electrical currents on the third lines.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: March 8, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Patent number: 11257555
    Abstract: The present invention relates to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. Each bit in each index word is associated with a physical address for a physical word in the emulated EEPROM, and the index word keeps track of which physical word is the current word for a particular logical address. The use of the index word enables a wear leveling algorithm that allows for a programming command to a logical address to result in: (i) skipping the programming operation if the data stored in the current word does not contain a “1” that corresponds to a “0” in the data to be stored, (ii) reprogramming one or more bits of the current word in certain situations, or (iii) shifting to and programming the next physical word in certain situations.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: February 22, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Guangming Lin, Xiaozhou Qian, Xiao Yan Pi, Vipin Tiwari, Zhenlin Ding
  • Publication number: 20210407588
    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.
    Type: Application
    Filed: September 9, 2021
    Publication date: December 30, 2021
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Patent number: 11188237
    Abstract: Multiple embodiments are disclosed for enhancing security and preventing hacking of a flash memory device. The embodiments prevent malicious actors from hacking a flash memory chip to obtain data that is stored within the chip. The embodiments include the use of fault detection circuits, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: November 30, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do
  • Publication number: 20210358551
    Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using a tuning mechanism. This achieves extreme programming accuracy and programming speed.
    Type: Application
    Filed: October 28, 2020
    Publication date: November 18, 2021
    Inventors: HIEU VAN TRAN, STANLEY HONG, STEPHEN TRINH, THUAN VU, STEVEN LEMKE, VIPIN TIWARI, NHAN DO
  • Publication number: 20210350217
    Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground expeditiously. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation.
    Type: Application
    Filed: November 5, 2020
    Publication date: November 11, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Vipin Tiwari, Han Tran, Hien Pham
  • Patent number: 11158374
    Abstract: Numerous embodiments are disclosed for providing temperature compensation in a an analog memory array. The analog memory array optionally is a vector-by-matrix multiplier in an analog neuromorphic memory system used in a deep learning neural network. One embodiment comprises measuring an operating temperature within a memory array and applying, by a temperature compensation block, a bias voltage to a terminal of a memory cell in the array, wherein the bias voltage is a function of the operating temperature.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: October 26, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Nhan Do, Vipin Tiwari, Mark Reiten
  • Publication number: 20210295907
    Abstract: Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. High voltage circuits used to generate high voltages applied to terminals of the non-volatile memory cells during the precision tuning process are also disclosed. Programming sequences for the application of the voltages to the terminals to minimize the occurrence of disturbances during tuning are also disclosed.
    Type: Application
    Filed: September 17, 2020
    Publication date: September 23, 2021
    Inventors: HIEU VAN TRAN, THUAN VU, STEPHEN TRINH, STANLEY HONG, ANH LY, STEVEN LEMKE, VIPIN TIWARI, NHAN DO
  • Publication number: 20210287065
    Abstract: A number of circuits for use in an output block coupled to a non-volatile memory array in a neural network are disclosed. The embodiments include a circuit for converting an output current from a neuron in a neural network into an output voltage, a circuit for converting a voltage received on an input node into an output current, a circuit for summing current received from a plurality of neurons in a neural network, and a circuit for summing current received from a plurality of neurons in a neural network.
    Type: Application
    Filed: April 22, 2021
    Publication date: September 16, 2021
    Inventors: Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten